skip to main content
research-article

Combined WCET analysis of bitcode and machine code using control-flow relation graphs

Published:20 June 2013Publication History
Skip Abstract Section

Abstract

Static program analyses like stack usage analysis and worst-case execution time (WCET) analysis depend on the actual machine code generated by the compiler for the target system. As the analysis of binary code is costly, hard to diagnose and platform dependent, it is preferable to carry out parts of these analyses on a higher-level program representation. To this end, the higher-level code and the machine code need to be related, a difficult task due to the complexity of modern optimizing compilers.

In this article, we present a novel representation called control-flow relation graphs, which provide an accurate model of the control-flow relation between machine code and the compiler's intermediate representation. In order to facilitate the integration of our approach in existing compiler frameworks, we develop a construction algorithm that builds the control-flow relation graph from partial mappings provided by the compiler. The WCET calculation method for control-flow relation graphs processes flow information from both the intermediate representation and machine code. Furthermore, we demonstrate the transformation of flow information from the IR to the machine code level, in order to use existing industrial-strength WCET analysis tools operating on machine code. We implemented the construction algorithm within the LLVM compiler framework, along with an implementation of the combined WCET calculation method.

The evaluation demonstrates that the approach is able to relate bitcode (LLVM's intermediate representation) and machine code in a precise way, with a WCET increase of at most 2% when using flow facts on the bitcode level, compared to equivalent ones on the machine-code level. As the methods presented in this article provide a cost-effective way to reuse platform independent flow information, they have the potential to simplify WCET analysis, and popularize its use in the development process of real-time systems.

References

  1. R. L. Bernstein. Producing good code for the case statement. Software: Practice and Experience, 15 (10): 1021--1024, 1985. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. J. Berstel. Transductions and context-free languages, volume 4. Teubner Stuttgart, 1979.Google ScholarGoogle Scholar
  3. A. Bouchhima, P. Gerin, and F. Petrot. Automatic instrumentation of embedded software for high level hardware/software co-simulation. In Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific, pages 546--551, Jan. 2009. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. A. R. Bradley and Z. Manna. The Calculus of Computation: Decision Procedures with Applications to Verification. Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2007. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. J. Engblom, A. Ermedahl, and P. Altenbernd. Facilitating worst-case execution times analysis for optimized code. In Proceedings of the 10th Euromicro Workshop on Real-Time Systems, pages 146--153, June 1998.Google ScholarGoogle ScholarCross RefCross Ref
  6. H. Falk and P. Lokuciejewski. A compiler framework for the reduction of worst-case execution times. Real-Time Systems, pages 1--50, 2010. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. J. Gustafsson, A. Ermedahl, C. Sandberg, and B. Lisper. Automatic derivation of loop bounds and infeasible paths for wcet analysis using abstract execution. In Proceedings of the 27th IEEE International Real-Time Systems Symposium, RTSS, pages 57--66, Washington, DC, USA, 2006. IEEE Computer Society. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper. The Mälardalen WCET benchmarks -- past, present and future. pages 137--147, Brussels, Belgium, July 2010. OCG.Google ScholarGoogle Scholar
  9. R. Kirner, P. Puschner, and A. Prantl. Transforming flow information during code optimization for timing analysis. Real-Time Systems, 45: 72--105, 2010. ISSN 0922--6443. 10.1007/s11241-010--9091--8. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. C. Lattner and V. Adve. LLVM: a compilation framework for lifelong program analysis transformation. In Code Generation and Optimization, 2004. CGO 2004. International Symposium on, pages 75--86, march 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. A. Mok, P. Amerasinghe, M. Chen, and K. Tantisirivat. Evaluating tight execution time bounds of programs by annotations. IEEE Real-Time Syst. Newsl., 5 (2--3): 81--86, May 1989. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. G. C. Necula. Translation validation for an optimizing compiler. In Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, PLDI '00, pages 83--94, New York, NY, USA, 2000. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. P. P. Puschner and A. V. Schedl. Computing maximum task execution times - a graph-based approach. Real-Time Systems, 13 (1): 67--91, 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. J. Schnerr, O. Bringmann, A. Viehl, and W. Rosenstiel. High-performance timing simulation of embedded software. In Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, pages 290 --295, june 2008. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. M. Schoeberl, T. B. Preußer, and S. Uhrig. The embedded Java benchmark suite JemBench. In phProceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES'10, pages 120--127, New York, NY, USA, 2010. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner, C. W. Probst, S. Karlsson, and T. Thorn. Towards a time-predictable dual-issue microprocessor: The Patmos approach. In phFirst Workshop on Bringing Theory to Practice: Predictability and Performance in Embedded Systems (PPES 2011), pages 11--20, March 2011.Google ScholarGoogle Scholar
  17. C. Sinz, F. Merz, and S. Falke. LLBMC: A bounded model checker for LLVM's intermediate representation (competition contribution). In C. Flanagan and B. König, editors, phProceedings of the 18th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'12), pages 542--544. Springer-Verlag, 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. S. Stattelmann, O. Bringmann, and W. Rosenstiel. Dominator homomorphism based code matching for source-level simulation of embedded software. In Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '11, pages 305?--314, New York, NY, USA, 2011. ACM. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. S. Stattelmann, G. Gebhard, C. Cullmann, O. Bringmann, and W. Rosenstiel. Hybrid source-level simulation of data caches using abstract cache models. In Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pages 376--381, Mar. 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. R. E. Tarjan. A unified approach to path problems. J. ACM, 28 (3): 577--593, July 1981. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. H. Theiling, C. Ferdinand, and R. Wilhelm. Fast and precise WCET prediction by separate cache and path analyses. Real-Time Systems, 18 (2/3), 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. Z. Wang and J. Henkel. Accurate source-level simulation of embedded software with respect to compiler optimizations. In Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pages 382 --387, Mar. 2012. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. F. Zuleger, S. Gulwani, M. Sinn, and H. Veith. Bound analysis of imperative programs with the size-change abstraction. In E. Yahav, editor, phStatic Analysis, volume 6887 of Lecture Notes in Computer Science, pages 280--297. Springer Berlin / Heidelberg, 2011. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Combined WCET analysis of bitcode and machine code using control-flow relation graphs

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in

    Full Access

    • Published in

      cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 48, Issue 5
      LCTES '13
      May 2013
      165 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/2499369
      Issue’s Table of Contents
      • cover image ACM Conferences
        LCTES '13: Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
        June 2013
        184 pages
        ISBN:9781450320856
        DOI:10.1145/2491899

      Copyright © 2013 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 20 June 2013

      Check for updates

      Qualifiers

      • research-article

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader