research-article

Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices

Authors:

Hai LiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18, Issue 4

Article No.: 57, Pages 1 - 18

https://doi.org/10.1145/2500459

Published: 25 October 2013 Publication History

Abstract

Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck for further density improvement. In this article we propose a novel common-source-line array architecture, which uses a shared source-line along the row, leaving only one bitline per column. We elaborate the array design to ensure reliability, and demonstrate its effectiveness on STT-MRAM and memristor memory arrays. Our study results show that with comparable latency and energy, the proposed common-source-line array can save 34% and 33% area for Memristor-RAM and STT-MRAM respectively, compared with corresponding dual-bitline arrays.

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Alishzadeh YJassbi SReshadi M(2023)Energy management of fault-tolerant real-time embedded systems through switching-activity-based techniquesMicroprocessors and Microsystems10.1016/j.micpro.2023.104929102(104929)Online publication date: Oct-2023
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Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 18, Issue 4

Special Section on Networks on Chip: Architecture, Tools, and Methodologies

October 2013

380 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2541012

Issue’s Table of Contents

Copyright © 2013 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 25 October 2013

Accepted: 01 June 2013

Revised: 01 March 2013

Received: 01 December 2012

Published in TODAES Volume 18, Issue 4

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https://doi.org/10.1016/j.micpro.2023.104929
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https://doi.org/10.1142/S0218126620502035
Wang CFeng DTong WLiu JLi ZChang JZhang YWu BXu JZhao WLi YRen R(2019)Cross-point Resistive MemoryACM Transactions on Design Automation of Electronic Systems10.1145/332506724:4(1-37)Online publication date: 20-Jun-2019
https://dl.acm.org/doi/10.1145/3325067
Hamdioui SFieback MNagarajan STaouil M(2019)Testing Computation-in-Memory Architectures Based on Emerging Memories2019 IEEE International Test Conference (ITC)10.1109/ITC44170.2019.9000117(1-10)Online publication date: Nov-2019
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Jiang LZhao BYang JZhang Y(2015)Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM TechnologyACM Transactions on Design Automation of Electronic Systems10.1145/276490320:4(1-24)Online publication date: 28-Sep-2015
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Zhang XZhao LZhang YYang J(2015)Exploit common source-line to construct energy efficient domain wall memory based cachesProceedings of the 2015 33rd IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2015.7357097(157-163)Online publication date: 18-Oct-2015
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Yi Wang Min Huang Zili Shao Chan HBathen LDutt N(2014)A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.234792933:11(1623-1631)Online publication date: Nov-2014
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