FPGAWORLD

This paper presents our experiences in using FPGA in teaching System-on-Chip design in Tampere University of Technology. We had a major reform on our courses and, most notably, chose a common HW platform which is used in 11 courses. It has proved good ...

The paper presents a new concept of creating an energy and computation effective AdaBoost classifier systems. The presented method is mainly novel in the way how it divides and accelerates an AdaBoost classifier into two parts -- a pre-processing and a ...

We describe the design and exploration methodology to optimize 3-dimensional (3D) Heterogeneous Tree-based FPGAs (HT-FPGAs) by introducing a break-point at a particular tree level interconnect to optimize the speed, power consumption and area. The ...

High throughput applications have been widely used for deployment onto FPGAs. As the requirements for performance increase so does the challenge of integrating more complex algorithms into these platforms. This paper presents a flexible, low resource ...

Cooperation of CPU and hardware accelerator to accomplish computational intensive tasks, provides significant advantages in run-time speed and energy. Efficient management of data sharing among multiple computational kernels can rapidly turn into a ...

Voltage and frequency adaptation can be used to create energy proportional systems in which energy usage adapts to the amount of work to be done in the available time. Closed-loop voltage and frequency scaling can also take into account process and ...

Designing a SoC for applications with mixed time-criticality is a complex and time-consuming task. Even when SoCs are built from components with known real-time properties, they still have to be combined and configured correctly to assert that these ...

Network-on-Chip (NoC) is an alternative to traditional busses for faster interconnect mechanism. The aim is to have infinite scalability, and this implies the possibility to extend the on-chip NoC communication protocol off-chip. To gain wholesome ...

This work reviews the contributions of power-oriented pipelining over the last two decades, and adds up-to-date results on 65 nm and 45 nm FPGAs. The data show that power consumption can be reduced by a factor between 0.1 and 0.8 using different levels ...

Data-rate of wireless links are increasing fast, particularly when new carrier bands with very high bandwidth becomes available. Utilizing the full bandwidth for a single carrier facilitates very large baud-rates. When the baud-rates approaches or ...