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Energy proportional computing in commercial FPGAs with adaptive voltage scaling

Published: 10 September 2013 Publication History

Abstract

Voltage and frequency adaptation can be used to create energy proportional systems in which energy usage adapts to the amount of work to be done in the available time. Closed-loop voltage and frequency scaling can also take into account process and temperature variations in addition to system load and this removes a significant proportion of the margins used by device manufacturers. This paper explores the capabilities of commercial FPGAs to use closed-loop adaptive voltage scaling to improve their energy and performance profiles beyond nominal. An adaptive power architecture based on a modified design flow is created with in-situ detectors and dynamic reconfiguration of clock management resources. The results of deploying AVS in FPGAs shows power and energy savings exceeding 85% compared with nominal voltage operation at the same frequency or 100% better performance at nominal energy. The in-situ detector approach compares favorably with critical path replication based on delay lines since it avoids the need of cumbersome and error-prone delay line calibration.

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  1. Energy proportional computing in commercial FPGAs with adaptive voltage scaling

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    cover image ACM Other conferences
    FPGAworld '13: Proceedings of the 10th FPGAworld Conference
    September 2013
    75 pages
    ISBN:9781450324960
    DOI:10.1145/2513683
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Published: 10 September 2013

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    Author Tags

    1. AVS
    2. DVFS
    3. FPGA
    4. energy efficiency

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    FPGAWorld '13
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    FPGAWorld '13: FPGAworld Conference
    September 10 - 12, 2013
    Stockholm, Sweden

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    Overall Acceptance Rate 4 of 6 submissions, 67%

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    Cited By

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    • (2019)FRoC 2.0ACM Transactions on Reconfigurable Technology and Systems10.1145/335418812:4(1-28)Online publication date: 9-Sep-2019
    • (2019)Energy‐efficient operation of a network of OpenFlow switches featuring hardware acceleration and frequency scalingTransactions on Emerging Telecommunications Technologies10.1002/ett.3619(e3619)Online publication date: 2-May-2019
    • (2018)Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.280122237:12(3095-3108)Online publication date: Dec-2018
    • (2018)Automatic BRAM Testing for Robust Dynamic Voltage Scaling for FPGAs2018 28th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2018.00020(68-687)Online publication date: Aug-2018
    • (2017)Sketching Computation with Stochastic Processing EnginesACM Journal on Emerging Technologies in Computing Systems10.1145/300765213:3(1-19)Online publication date: 14-Apr-2017
    • (2016)Measure twice and cut once: Robust dynamic voltage scaling for FPGAs2016 26th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2016.7577342(1-11)Online publication date: Aug-2016
    • (2014)Energy-efficient imprecise reconfigurable computing through probabilistic domain transformation2014 IEEE Dallas Circuits and Systems Conference (DCAS)10.1109/DCAS.2014.6965329(1-4)Online publication date: Oct-2014
    • (2014)A survey of power and energy efficient techniques for high performance numerical linear algebra operationsParallel Computing10.1016/j.parco.2014.09.00140:10(559-573)Online publication date: 1-Dec-2014

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