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ForEVeR: A complementary formal and runtime verification approach to correct NoC functionality

Published: 28 March 2014 Publication History

Abstract

As silicon technology scales, modern processor and embedded systems are rapidly shifting towards complex chip multi-processor (CMP) and system-on-chip (SoC) designs. As a side effect of complexity of these designs, ensuring their correctness has become increasingly problematic. Within these domains, Network-on-Chips (NoCs) are a de-facto choice to implement on-chip interconnect; their design is quickly becoming extremely complex in order to keep up with communication performance demands. As a result, design errors in the NoC may go undetected and escape into the final silicon.
In this work, we propose ForEVeR, a solution that complements the use of formal methods and runtime verification to ensure functional correctness in NoCs. Formal verification, due to its scalability limitations, is used to verify smaller modules, such as individual router components. To deliver correctness guarantees for the complete network, we propose a network-level detection and recovery solution that monitors the traffic in the NoC and protects it against escaped functional bugs. To this end, ForEVeR augments the baseline NoC with a lightweight checker network that alerts destination nodes of incoming packets ahead of time. If a bug is detected, flagged by missed packet arrivals, our recovery mechanism delivers the in-flight data safely to the intended destination via the checker network. ForEVeR's experimental evaluation shows that it can recover from NoC design errors at only 4.9% area cost for an 8x8 mesh interconnect, over a time interval ranging from 0.5K to 30K cycles per recovery event, and it incurs no performance overhead in the absence of errors. ForEVeR can also protect NoC operations against soft-errors: a growing concern with the scaling of silicon. ForEVeR leverages the same monitoring hardware to detect soft-error manifestations, in addition to design-errors. Recovery of the soft-error affected packets is guaranteed by building resiliency features into our checker network. ForEVeR incurs minimal performance penalty up to a flit error rate of 0.01% in lightly loaded networks.

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    Published In

    cover image ACM Transactions on Embedded Computing Systems
    ACM Transactions on Embedded Computing Systems  Volume 13, Issue 3s
    Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
    March 2014
    403 pages
    ISSN:1539-9087
    EISSN:1558-3465
    DOI:10.1145/2597868
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Publication History

    Published: 28 March 2014
    Accepted: 01 August 2013
    Revised: 01 May 2013
    Received: 01 December 2012
    Published in TECS Volume 13, Issue 3s

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    Author Tags

    1. Network-on-chip
    2. NoC
    3. formal verification
    4. functional correctness
    5. runtime verification

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    • (2022)Network-on-Chip Trust Validation Using Security AssertionsJournal of Hardware and Systems Security10.1007/s41635-022-00129-56:3-4(79-94)Online publication date: 7-Dec-2022
    • (2021)Network-on-Chip Security and Trust VerificationNetwork-on-Chip Security and Privacy10.1007/978-3-030-69131-8_12(311-337)Online publication date: 22-Jan-2021
    • (2018)Monitor and Knob Techniques in Network-on-Chip ArchitecturesHarnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms10.1007/978-3-319-91962-1_9(187-213)Online publication date: 24-Oct-2018
    • (2016)An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip ArchitecturesACM Transactions on Architecture and Code Optimization10.1145/293067013:2(1-26)Online publication date: 14-Jun-2016
    • (2016)Secure Model Checkers for Network-on-Chip (NoC) ArchitecturesProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2903032(45-50)Online publication date: 18-May-2016
    • (2014)Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN2014 International Symposium on System-on-Chip (SoC)10.1109/ISSOC.2014.6972449(1-8)Online publication date: Oct-2014
    • (2014)Adaptive runtime management of heterogenous MPSoCs: Analysis, acceleration and silicon prototype2014 International Symposium on System-on-Chip (SoC)10.1109/ISSOC.2014.6972444(1-4)Online publication date: Oct-2014
    • (2014)L2_ISA++: Instruction set architecture extensions for 4G and LTE-advanced MPSoCs2014 International Symposium on System-on-Chip (SoC)10.1109/ISSOC.2014.6972439(1-8)Online publication date: Oct-2014

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