2013 Proceeding- General Chairs:
- Kirk Cameron,
- Darren Kerbyson,
- Andres Marquez,
- Dimitrios S. Nikolopoulos,
- Sudha Yalamanchili,
- Program Chair:
- Kevin Barker
With Exascale systems on the horizon, we will be ushering in an era with power and energy consumption as the primary concerns for scalable computing. To achieve viable high performance, revolutionary methods are required with a stronger integration among hardware features, system software and applications. Equally important are the capabilities for fine-grained spatial and temporal measurement and control to facilitate energy efficient computing across all layers. Current approaches for energy efficient computing rely heavily on power efficient hardware in isolation. However, it is pivotal for hardware to expose mechanisms for energy efficiency to optimize power and energy consumption for various workloads and to reduce data motion, a major component of energy use. At the same time, high fidelity measurement techniques, typically ignored in data-center level measurement, are of high importance for scalable and energy efficient inter-play in different layers of application, system software and hardware.
Proceeding Downloads
Initial investigation of a scheme to use instantaneous CPU power consumption for energy savings format
The drive to extract peak performance from the modern computing platforms has lead to drastic increase in their energy and power consumption and thereby affecting the operating costs and failure rates. Modern processors provide techniques, such as ...
Toward application-specific memory reconfiguration for energy efficiency
The end of Dennard scaling has made energy-efficiency a critical challenge in the continued increase of computing performance. An important approach to increasing energy-efficiency is hardware customization. In this study we explore the opportunity for ...
Modeling the effects of DFS on power consumption in hybrid chip multiprocessors
The power wall is one of the primary stumbling blocks that many-core microprocessor architecture is facing today. To avoid this problem, microprocessor makers are shifting towards heterogeneous chips that integrate different core architectures on a ...
Unified performance and power modeling of scientific workloads
It is expected that scientific applications executing on future large-scale HPC must be optimized not only in terms of performance, but also in terms of power consumption. As power and energy become increasingly constrained resources, researchers and ...
Leakage energy estimates for HPC applications
Large-scale high-performance systems are energy constrained. With thousands of processing cores at their disposal, these machines contain large amounts of on-chip caches. With a trend of decreasing thresholds in transistors, the amount of leakage ...
Evaluating energy savings for checkpoint/restart
The U. S. Department of Energy has identified resilience and energy consumption as key challenges for future extreme-scale systems. All checkpoint/restart methods require I/O to local or remote storage. Efforts are under way to minimize the amount of ...
OpenMP and MPI application energy measurement variation
Power, energy, and compute time are all important metrics that can act as either objectives or constraints in program or system optimization. Recent microprocessors include sensors (counters) for monitoring these metrics as well as on-chip system ...