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On heterogeneous network-on-chip design based on constraint programming

Published: 08 December 2013 Publication History

Abstract

Core mapping and application scheduling problems coupled with routing schemes are essential design considerations for an efficient Network-on-Chip (NoC) design. This paper discusses heterogeneous NoC design from a Constraint Programming (CP) perspective using a two-stage solution. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage in order to minimize the overall communication cost among cores. We then solve the application scheduling problem in the second stage to determine the optimum core types from a list of technological alternatives and to minimize the makespan i.e. time to complete all tasks. As a design extension, surface area constraint can be introduced to the underlying problem. The paper reports results based on real benchmark datasets from the literature.

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Cited By

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  • (2020)Temperature-Aware Core Mapping for Heterogeneous 3D NoC Design Through Constraint Programming2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00054(312-318)Online publication date: Mar-2020
  • (2014)Voltage island based heterogeneous NoC design through constraint programmingComputers and Electrical Engineering10.1016/j.compeleceng.2014.08.00540:8(307-316)Online publication date: 1-Nov-2014

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cover image ACM Other conferences
NoCArc '13: Proceedings of the Sixth International Workshop on Network on Chip Architectures
December 2013
72 pages
ISBN:9781450323703
DOI:10.1145/2536522
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 08 December 2013

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NoCArc '13
NoCArc '13: Network on Chip Architectures
December 8, 2013
California, Davis, USA

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  • (2020)Temperature-Aware Core Mapping for Heterogeneous 3D NoC Design Through Constraint Programming2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)10.1109/PDP50117.2020.00054(312-318)Online publication date: Mar-2020
  • (2014)Voltage island based heterogeneous NoC design through constraint programmingComputers and Electrical Engineering10.1016/j.compeleceng.2014.08.00540:8(307-316)Online publication date: 1-Nov-2014

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