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On multicast for dynamic and irregular on-chip networks using dynamic programming method

Published: 08 December 2013 Publication History

Abstract

Mutlicast is an intrinsic communication pattern in emerging applications including the Internet service, bio-inspired computing, online data analysis, etc. Providing hardware multicast largely boosts system performance and reduce power consumption for these applications running on many-core systems. However, many-core systems suffer from dynamically changing topologies, which can be caused by traffic isolation, power management and faults. Links and routers may be removed from a subnetwork or added to a subnetwork, this imposes the routers to alter the routing paths accordingly to make the routing energy efficient. Furthermore an energy efficient multicast scheme that fits to any topology is required in this scenario. Most existing fault tolerant routings cannot detect and found energy efficient communication paths effectively for both unicast and multicast. In this work, a lightweight network couples with on-chip routers is used to propagates topological information. The shortest path between any node pair is also computed in this network using dynamic programming method. Unicast packets are routed along a shortest path to its destination, and multicast packet copies at each router is minimized based a rule called minimal replication to reduce multicast link occupation and energy consumption. Simulation results show that the proposed NoC routes 96% packets to their destinations if there exists a path, and demonstrate 40% lower latency and 30% power consumption compared with Stochastic communication. The extra hardware cost to build optimal multicast path is estimated to occupy less than 5% of the total area of a router.

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Cited By

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  • (2015)Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-ChipVLSI-SoC: Internet of Things Foundations10.1007/978-3-319-25279-7_1(1-20)Online publication date: 25-Nov-2015
  • (2014)Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2014.7004156(1-6)Online publication date: Oct-2014

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cover image ACM Other conferences
NoCArc '13: Proceedings of the Sixth International Workshop on Network on Chip Architectures
December 2013
72 pages
ISBN:9781450323703
DOI:10.1145/2536522
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 08 December 2013

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NoCArc '13
NoCArc '13: Network on Chip Architectures
December 8, 2013
California, Davis, USA

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Overall Acceptance Rate 46 of 122 submissions, 38%

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View all
  • (2015)Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-ChipVLSI-SoC: Internet of Things Foundations10.1007/978-3-319-25279-7_1(1-20)Online publication date: 25-Nov-2015
  • (2014)Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-Chip2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2014.7004156(1-6)Online publication date: Oct-2014

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