skip to main content
10.1145/2536522.2536534acmotherconferencesArticle/Chapter ViewAbstractPublication PagesmicroConference Proceedingsconference-collections
research-article

Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth

Published: 08 December 2013 Publication History

Abstract

3D NoC is one of the most promising technologies that can overcome the performance barrier of traditional multi-core system. While TSV is the most popular method to realize vertical link for 3D IC, it has many fabrication challenges and the number of TSVs can be limited in practice, thereby limiting vertical bandwidth. Some adaptive routing algorithms have been studied to overcome the bandwidth mismatch. However, there has been no previous study on how much improvement can be achieved by such new algorithms. This paper explores 3D NoC's performance upper-bound beyond which we believe no practically realizable algorithm can reach. We also propose a practically realizable algorithm that achieves performance close to the upper-bound.

References

[1]
Dally, W. J., and Towles, B., 2001, Route packets, not wires: on-chip interconnection networks, In Proc. DAC, 684--689.
[2]
The TILE-GxTM processor family, Tilera, 2009, http://www.tilera.com/products/processors.
[3]
Epiphany, Adapteva, 2012, http://www.adapteva.com/products/epiphany-ip/epiphany-architecture-ip/.
[4]
Wentzlaff, D., Griffin, P., Hoffmann, H., Bao, L., Edwards, B., Ramey, C., Mattina, M., Miao, C.-C., Brown, J. F. and Agarwal, A., 2007, On-chip interconnection architecture of the tile processor, IEEE Micro, 27, 5, 15--31.
[5]
Feero, B. S., and Pande, P. P., 2009, Networks-on-chip in a three-dimensional environment: a performance evaluation, IEEE Trans. Computers, 58, 1, 32--45.
[6]
Fallin, C., Nazario, G., Yu, X., Chang. K., Ausavarungnirun, R., and Mutlu, O., 2012, MinBD: minimally-buffered deflection routing for energy-efficient interconnect, In Proc. NOCS, 1--10.
[7]
Vangal, S., Howard, J., Ruhl, G., and Dighe, S. et al., 2007, An 80-tile 1.28 TFLOPS network-on-chip in 65nm CMOS, In Proc. ISSCC, 98--589.
[8]
Zhu, M., Lee, J., and Choi, K., 2012, An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth, In Proc. VLSI-SOC, 18--23.
[9]
Duato, J., 1993, A new theory of deadlock-free adaptive routing in wormhole networks, IEEE Trans. Parallel and Distributed Systems, 4, 12, 1320--1331.
[10]
Duato, J., 1995, A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks, IEEE Trans. Parallel and Distributed Systems, 6, 10, 1055--1067.
[11]
Glass, C. J., 1992, The turn model for adaptive routing, In Proc. ISCA, 278--287.
[12]
Chiu, G.-M., 2000, The odd-even turn model for adaptive routing, IEEE Trans. Parallel and Distributed Systems, 11, 7, 729--738.
[13]
Dally, W. J., 1992, Virtual-channel flow control, IEEE Trans. Parallel and Distributed Systems, 3, 2, 194--205.
[14]
Scott, S. L., Thorson, G. M., 1996, The Cray T3E network: adaptive routing in a high performance 3D torus, HOT Interconnects IV, Stanford University.
[15]
Rahmani, A.--M., Latif, K., Vaddina, K. R., Liljeberg. P. et al., 2012, ARB-NET: a novel adaptive monitoring platform for stacked mesh 3D NoC architectures, In Proc. ASP-DAC, 413--418.
[16]
Kagami, T., Matsutani, H., Koibuchi, M., and Amano, H., 2013, Headfirst sliding routing: a time-based routing scheme for bus-NoC hybrid 3-D architecture, In Proc. NOCS, 1--8.
[17]
Dally, W. J., and Seitz, C. L., 1993, Deadlock-free adaptive routing in multicomputer networks using virtual channels, IEEE Trans. Parallel and Distributed Systems, 4, 4, 466--475.
[18]
Kim, H. S., and Leon-Garcia, A., 1990, A self-routing multistage switching network for broadband ISDN, IEEE Journal on Selected Areas in Communications, 8, 3, 459--466.

Index Terms

  1. Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Other conferences
      NoCArc '13: Proceedings of the Sixth International Workshop on Network on Chip Architectures
      December 2013
      72 pages
      ISBN:9781450323703
      DOI:10.1145/2536522
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 08 December 2013

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. network-on-chip
      2. routing algorithm
      3. through silicon via

      Qualifiers

      • Research-article

      Funding Sources

      Conference

      NoCArc '13
      NoCArc '13: Network on Chip Architectures
      December 8, 2013
      California, Davis, USA

      Acceptance Rates

      Overall Acceptance Rate 46 of 122 submissions, 38%

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • 0
        Total Citations
      • 145
        Total Downloads
      • Downloads (Last 12 months)3
      • Downloads (Last 6 weeks)0
      Reflects downloads up to 19 Feb 2025

      Other Metrics

      Citations

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media