skip to main content
10.1145/2541940.2541950acmconferencesArticle/Chapter ViewAbstractPublication PagesasplosConference Proceedingsconference-collections
research-article

The sharing architecture: sub-core configurability for IaaS clouds

Published: 24 February 2014 Publication History

Abstract

Businesses and Academics are increasingly turning to Infrastructure as a Service (IaaS) Clouds such as Amazon's Elastic Compute Cloud (EC2) to fulfill their computing needs. Unfortunately, current IaaS systems provide a severely restricted pallet of rentable computing options which do not optimally fit the workloads that they are executing. We address this challenge by proposing and evaluating a manycore architecture, called the Sharing Architecture, specifically optimized for IaaS systems by being reconfigurable on a sub-core basis. The Sharing Architecture enables better matching of workload to micro-architecture resources by replacing static cores with Virtual Cores which can be dynamically reconfigured to have different numbers of ALUs and amount of Cache. This reconfigurability enables many of the same benefits of heterogeneous multicores, but in a homogeneous fabric, and enables the reuse and resale of resources on a per ALU or per KB of cache basis. The Sharing Architecture leverages Distributed ILP techniques, but is designed in a way to be independent of recompilation. In addition, we introduce an economic model which is enabled by the Sharing Architecture and show how different users who have varying needs can be better served by such a flexible architecture. We evaluate the Sharing Architecture across a benchmark suite of Apache, SPECint, and parts of PARSEC, and find that it can achieve up to a 5x more economically efficient market when compared to static architecture multicores. We implemented the Sharing Architecture in Verilog and present area overhead results.

References

[1]
Amazon elastic compute cloud. http://aws.amazon.com/ec2/.
[2]
Google Apps. http://www.google.com/apps/business/index.html.
[3]
Amazon simple storage service. http://aws.amazon.com/s3/.
[4]
Windows Azure Platform, 2009. http://www.microsoft.com/azure/.
[5]
A. Ali-Eldin, J. Tordsson, and E. Elmroth. An adaptive hybrid elasticity controller for cloud infrastructures. In Network Operations and Management Symposium (NOMS), 2012 IEEE, pages 204--212, 2012.
[6]
J. Ansel, M. Pacula, Y. L. Wong, C. Chan, M. Olszewski, U.-M. O'Reilly, and S. Amarasinghe. Siblingrivalry: online autotuning through local competitions. In Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems, CASES '12, pages 91--100, 2012.
[7]
M. Armbrust, A. Fox, R. Griffith, A. D. Joseph, R. H. Katz, A. Konwinski, G. Lee, D. A. Patterson, A. Rabkin, and M. Zaharia. Above the Clouds: A Berkeley View of Cloud Computing. Technical Report UCB/EECS-2009-28, EECS Department, University of California, Berkeley, Feb 2009.
[8]
R. Balasubramonian, S. Dwarkadas, and D. Albonesi. Dynamically managing the communication-parallelism trade-off in future clustered processors. In Computer Architecture, 2003. Proceedings. 30th Annual International Symposium on, pages 275--286, june 2003.
[9]
J. Barr. Amazon Web Services Blog, January 28, 201, January 28, 20111. http://aws.typepad.com/aws/2011/01/amazon-s3-bigger-and-busier-than-ever.ht%ml.
[10]
N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. The GEM5 simulator. SIGARCH Comput. Archit. News, 39 (2): 1--7, Aug. 2011. ISSN 0163-5964.
[11]
D. Burger, S. Keckler, K. McKinley, M. Dahlin, L. John, C. Lin, C. Moore, J. Burrill, R. McDonald, and W. Yoder. Scaling to the end of silicon with EDGE architectures. Computer, 37 (7): 44--55, july 2004.
[12]
R. Buyya, C. S. Yeo, and S. Venugopal. Market-oriented cloud computing: Vision, hype, and reality for delivering it services as computing utilities. In Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications 2008.
[13]
J. Cong, A. Jagannathan, G. Reinman, and Y. Tamir. Understanding the energy efficiency of smt and cmp with multiclustering. In Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on, pages 48--53, 2005.
[14]
C. Delimitrou and C. Kozyrakis. Paragon: Qos-aware scheduling for heterogeneous datacenters. In Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems, ASPLOS '13, pages 77--88, New York, NY, USA, 2013.
[15]
Eucalyptus. Eucalyptus. http://www.eucalyptus.com/.
[16]
M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi. Clearing the Clouds: A Study of Emerging Scale-out Workloads on Modern Hardware. In 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2012.
[17]
P. Gratz, C. Kim, R. McDonald, S. Keckler, and D. Burger. Implementation and evaluation of on-chip network architectures. In Computer Design, 2006. ICCD 2006. International Conference on, pages 477--484, oct. 2006.
[18]
M. Guevara, B. Lubin, and B. C. Lee. Navigating heterogeneous processors with market mechanisms. In High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on, pages 95--106, 2013.
[19]
A. Gulati, G. Shanmuganathan, A. Holler, and I. Ahmad. Cloud-scale resource management: challenges and techniques. In Proceedings of the 3rd USENIX conference on Hot topics in cloud computing, HotCloud'11, pages 3--3, Berkeley, CA, USA, 2011.
[20]
F. Guo, Y. Solihin, L. Zhao, and R. Iyer. A framework for providing quality of service in chip multi-processors. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 40, pages 343--355, Washington, DC, USA, 2007.
[21]
B. Hindman, A. Konwinski, M. Zaharia, A. Ghodsi, A. D. Joseph, R. Katz, S. Shenker, and I. Stoica. Mesos: a platform for fine-grained resource sharing in the data center. In Proceedings of the 8th USENIX conference on Networked systems design and implementation, NSDI'11, pages 22--22, 2011.
[22]
H. Hoffmann, J. Eastep, M. D. Santambrogio, J. E. Miller, and A. Agarwal. Application heartbeats for software performance and health. In Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pages 347--348, 2010.
[23]
H. Hoffmann, M. Maggio, M. D. Santambrogio, A. Leva, and A. Agarwal. A generalized software framework for accurate and efficient managment of performance goals. In EMSOFT, 2013.
[24]
E. Ipek, M. Kirman, N. Kirman, and J. F. Martinez. Core Fusion: accommodating software diversity in chip multiprocessors. In Proceedings of the 34th annual international symposium on Computer architecture, pages 186--197, 2007.
[25]
M. Isard, V. Prabhakaran, J. Currey, U. Wieder, K. Talwar, and A. Goldberg. Quincy: fair scheduling for distributed computing clusters. In Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles, SOSP '09, pages 261--276, 2009.
[26]
R. Iyer, L. Zhao, F. Guo, R. Illikkal, S. Makineni, D. Newell, Y. Solihin, L. Hsu, and S. Reinhardt. Qos policies and architecture for cache/memory in cmp platforms. In Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, SIGMETRICS '07, pages 25--36, 2007.
[27]
V. Janapa Reddi, B. C. Lee, T. Chilimbi, and K. Vaid. Web search using mobile cores: quantifying and mitigating the price of efficiency. In Proceedings of the 37th annual international symposium on Computer architecture, ISCA '10, pages 314--325, 2010.
[28]
M. Kambadur, T. Moseley, R. Hank, and M. A. Kim. Measuring interference between live datacenter applications. In Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, SC '12, pages 51:1--51:12, 2012.
[29]
K. Khubaib, M. Suleman, M. Hashemi, C. Wilkerson, and Y. Patt. Morphcore: An energy-efficient microarchitecture for high performance ilp and high throughput tlp. In Microarchitecture (MICRO), 2012 45th Annual IEEE/ACM International Symposium on, pages 305--316, 2012.
[30]
C. Kim, S. Sethumadhavan, M. S. Govindan, N. Ranganathan, D. Gulati, D. Burger, and S. W. Keckler. Composable lightweight processors. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 40, pages 381--394, 2007. ISBN 0-7695-3047-8.
[31]
O. Krieger, P. McGachey, and A. Kanevsky. Enabling a marketplace of clouds: Vmware's vcloud director. SIGOPS Oper. Syst. Rev., 44 (4): 103--114, Dec. 2010. ISSN 0163-5980.
[32]
Kumar, Jouppi, and Tullsen}Kumar.2004.CCMR. Kumar, N. P. Jouppi, and D. M. Tullsen. Conjoined-core chip multiprocessing. In Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, MICRO 37, pages 195--206, 2004. ISBN 0-7695-2126-6.
[33]
R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-ISA heterogeneous multi-core architectures for multithreaded workload performance. In Computer Architecture, Proceedings. International Symposium on, pages 64--75, june 2004.
[34]
R. Kumar, D. Tullsen, N. Jouppi, and P. Ranganathan. Heterogeneous Chip Multiprocessors. Computer, 38 (11): 32--38, nov. 2005. ISSN 0018-9162. 10.1109/MC.2005.379.
[35]
R. M. Lerner. At the forge: Amazon web services. Linux J., 2006 (143): 12, 2006. ISSN 1075-3583.
[36]
Y. Li, D. Brooks, Z. Hu, K. Skadron, and P. Bose. Understanding the energy efficiency of simultaneous multithreading. In Low Power Electronics and Design, 2004. ISLPED '04. Proceedings of the 2004 International Symposium on, pages 44--49, 2004.
[37]
J. L. Lo, S. J. Eggers, J. S. Emer, H. M. Levy, R. L. Stamm, and D. M. Tullsen. Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading. ACM Trans. Comput. Syst., 15 (3): 322--354, Aug. 1997.
[38]
D. MacAskill. SkyNet Lives! (aka EC2 at SmugMug). http://don.blogs.smugmug.com/2008/06/03/skynet-lives-aka-ec2-smugmug/.
[39]
M. R. Marty and M. D. Hill. Virtual hierarchies to support server consolidation. In Proceedings of the 34th Annual International Symposium on Computer Architecture, ISCA '07, pages 46--56, 2007. ISBN 978-1-59593-706-3.
[40]
S. McFarling. Combining branch predictors. Technical Report TN-36, WRL Technical Note, 1993.
[41]
D. Meisner, C. M. Sadler, L. A. Barroso, W.-D. Weber, and T. F. Wenisch. Power management of online data-intensive services. In phProceedings of the 38th annual international symposium on Computer architecture, ISCA '11, pages 319--330, 2011.
[42]
Muralimanohar, Naveen, Balasubramonian, Rajeev, Jouppi, and N. P. Cacti 6.0: A tool to model large caches. Technical Report HPL-2009-85, HP Laboratories, 2009.
[43]
Openstack. Openstack Cloud Software. http://www.openstack.org/.
[44]
P. Padala, K.-Y. Hou, K. G. Shin, X. Zhu, M. Uysal, Z. Wang, S. Singhal, and A. Merchant. Automated control of multiple virtualized resources. In phProceedings of the 4th ACM European conference on Computer systems, EuroSys '09, pages 13--26, 2009.
[45]
S. Palacharla, N. P. Jouppi, and J. E. Smith. Complexity-effective superscalar processors. In Proceedings of the International Symposium on Computer Architecture, pages 206--218, June 1997.
[46]
M. R. Palankar, A. Iamnitchi, M. Ripeanu, and S. Garfinkel. Amazon S3 for science grids: a viable solution? In DADC '08: Proceedings of the 2008 international workshop on Dataaware distributed computing, pages 55--64, New York, NY, USA, 2008. ACM. ISBN 978-1-60558-154-5. http://doi.acm.org/10.1145/1383519.1383526.
[47]
M. K. Qureshi and Y. N. Patt. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 39, pages 423--432, 2006.
[48]
A. Ranadive, A. Gavrilovska, and K. Schwan. Resourceexchange: Latency-aware scheduling in virtualized environments with high performance fabrics. In Cluster Computing (CLUSTER), 2011 IEEE International Conference on, pages 45--53, 2011.
[49]
K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. Keckler, and C. Moore. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In Proceedings of the International Symposium on Computer Architecture, pages 422--433, 2003.
[50]
K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M. S. Govindan, P. Gratzf, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Shariff, P. Shivakumar, S. Keckler, and D. Burger. Distributed microarchitectural protocols in the TRIPS prototype processor. In Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International Symposium on, pages 480--491, dec. 2006.
[51]
M. Santambrogio, H. Hoffmann, J. Eastep, and A. Agarwal. Enabling technologies for self-aware adaptive systems. In Adaptive Hardware and Systems (AHS), 2010 NASA/ESA Conference on, pages 149--156, 2010.
[52]
B. Santithorn. Fully Distributed Register Files for Heterogeneous Clustered Mircroarchitectures. PhD thesis, Georgia Institute of Technology, 2005.
[53]
S. Sethumadhavan, R. McDonald, D. Burger, S. Keckler, and R. Desikan. Design and implementation of the TRIPS primary memory system. In Computer Design, 2006. ICCD 2006. International Conference on, pages 470--476, oct. 2006.
[54]
S. Sethumadhavan, F. Roesner, J. S. Emer, D. Burger, and S. W. Keckler. Late-binding: Enabling unordered load-store queues. In In Proceedings of the 34th Annual International symposium on Computer Architecture, pages 347--357, 2007.
[55]
Z. Shen, S. Subbiah, X. Gu, and J. Wilkes. Cloudscale: elastic resource scaling for multi-tenant cloud systems. In Proceedings of the 2nd ACM Symposium on Cloud Computing, SOCC '11, pages 5:1--5:14, 2011.
[56]
Y. Song, H. Wang, Y. Li, B. Feng, and Y. Sun. Multi-tiered on-demand resource scheduling for vm-based data center. In Proceedings of the 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid, CCGRID '09, pages 148--155, Washington, DC, USA, 2009.
[57]
G. Suh, S. Devadas, and L. Rudolph. A new memory monitoring scheme for memory-aware scheduling and partitioning. In High-Performance Computer Architecture, 2002. Proceedings. Eighth International Symposium on, pages 117--128, 2002.
[58]
S. Swanson, K. Michelson, A. Schwerin, and M. Oskin. Wavescalar. In Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, MICRO 36, pages 291--, 2003. ISBN 0-7695-2043-X.
[59]
M. Taylor, M. B. Taylor, W. Lee, S. Amarasinghe, and A. Agarwal. Scalar operand networks: on-chip interconnect for ilp in partitioned architectures. In High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on, pages 341--353, feb. 2003.
[60]
D. Tullsen, S. Eggers, and H. Levy. Simultaneous multithreading: maximizing on-chip parallelism. In Proceedings of the international symposium on Computer architecture, ISCA '95, pages 392--403, 1995.
[61]
VMWare. VMware Virtual Appliance Marketplace: Virtual Applications for the Cloud. http://www.vmware.com/appliances/.
[62]
T. von Eicken. Amazon Usage Estimates, RightScale Blog. http://blog.rightscale.com/2009/10/05/amazon-usage-estimates/.
[63]
E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring it all to software: Raw machines. Computer, 30 (9): 86--93, sep 1997.
[64]
Y. Watanabe, J. D. Davis, and D. A. Wood. WiDGET: Wisconsin decoupled grid execution tiles. SIGARCH Comput. Archit. News, 38 (3): 2--13, June 2010.
[65]
D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J. F. Brown III, and A. Agarwal. On-chip interconnection architecture of the Tile Processor. IEEE Micro, 27 (5): 15--31, Sept. 2007.

Cited By

View all
  • (2024)Monitoring Probe Deployment Patterns for Cloud-Native Applications: Definition and Empirical AssessmentIEEE Transactions on Services Computing10.1109/TSC.2024.334964817:4(1636-1654)Online publication date: Jul-2024
  • (2023)TMCProceedings of the 2023 ACM Symposium on Cloud Computing10.1145/3620678.3624667(376-393)Online publication date: 30-Oct-2023
  • (2022)Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319798041:11(3993-4003)Online publication date: Nov-2022
  • Show More Cited By

Index Terms

  1. The sharing architecture: sub-core configurability for IaaS clouds

      Recommendations

      Comments

      Information & Contributors

      Information

      Published In

      cover image ACM Conferences
      ASPLOS '14: Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
      February 2014
      780 pages
      ISBN:9781450323055
      DOI:10.1145/2541940
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

      Sponsors

      In-Cooperation

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 24 February 2014

      Permissions

      Request permissions for this article.

      Check for updates

      Author Tags

      1. cache
      2. cache banks
      3. infrastructure as a service (iaas)
      4. market efficiency
      5. slice
      6. utility
      7. virtual core (vcore)
      8. virtual machine (vm)

      Qualifiers

      • Research-article

      Conference

      ASPLOS '14

      Acceptance Rates

      ASPLOS '14 Paper Acceptance Rate 49 of 217 submissions, 23%;
      Overall Acceptance Rate 535 of 2,713 submissions, 20%

      Upcoming Conference

      Contributors

      Other Metrics

      Bibliometrics & Citations

      Bibliometrics

      Article Metrics

      • Downloads (Last 12 months)25
      • Downloads (Last 6 weeks)5
      Reflects downloads up to 28 Feb 2025

      Other Metrics

      Citations

      Cited By

      View all
      • (2024)Monitoring Probe Deployment Patterns for Cloud-Native Applications: Definition and Empirical AssessmentIEEE Transactions on Services Computing10.1109/TSC.2024.334964817:4(1636-1654)Online publication date: Jul-2024
      • (2023)TMCProceedings of the 2023 ACM Symposium on Cloud Computing10.1145/3620678.3624667(376-393)Online publication date: 30-Oct-2023
      • (2022)Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319798041:11(3993-4003)Online publication date: Nov-2022
      • (2020)CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO50266.2020.00060(650-664)Online publication date: Oct-2020
      • (2019)Enhancing Server Efficiency in the Face of Killer Microseconds2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00037(185-198)Online publication date: Feb-2019
      • (2019)Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2019.00024(15-27)Online publication date: Feb-2019
      • (2018)CABLEProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00033(312-325)Online publication date: 20-Oct-2018
      • (2017)CHARSTARACM SIGARCH Computer Architecture News10.1145/3140659.308021245:2(147-160)Online publication date: 24-Jun-2017
      • (2017)CHARSTARProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080212(147-160)Online publication date: 24-Jun-2017
      • (2017)Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.36(337-348)Online publication date: Feb-2017
      • Show More Cited By

      View Options

      Login options

      View options

      PDF

      View or Download as a PDF file.

      PDF

      eReader

      View online with eReader.

      eReader

      Figures

      Tables

      Media

      Share

      Share

      Share this Publication link

      Share on social media