research-article

The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism

Authors:

Lieven EeckhoutAuthors Info & Claims

ASPLOS '14: Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

Pages 591 - 606

https://doi.org/10.1145/2541940.2541954

Published: 24 February 2014 Publication History

Abstract

The number of active threads in a multi-core processor varies over time and is often much smaller than the number of supported hardware threads. This requires multi-core chip designs to balance core count and per-core performance. Low active thread counts benefit from a few big, high-performance cores, while high active thread counts benefit more from a sea of small, energy-efficient cores.

This paper comprehensively studies the trade-offs in multi-core design given dynamically varying active thread counts. We find that, under these workload conditions, a homogeneous multi-core processor, consisting of a few high-performance SMT cores, typically outperforms heterogeneous multi-cores consisting of a mix of big and small cores (without SMT), within the same power budget. We also show that a homogeneous multi-core performs almost as well as a heterogeneous multi-core that also implements SMT, as well as a dynamic multi-core, while being less complex to design and verify. Further, heterogeneous multi-cores that power-gate idle cores yield (only) slightly better energy-efficiency compared to homogeneous multi-cores.

The overall conclusion is that the benefit of SMT in the multi-core era is to provide flexibility with respect to the available thread-level parallelism. Consequently, homogeneous multi-cores with big SMT cores are competitive high-performance, energy-efficient design points for workloads with dynamically varying active thread counts.

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Index Terms

The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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cover image ACM Conferences

ASPLOS '14: Proceedings of the 19th international conference on Architectural support for programming languages and operating systems

February 2014

780 pages

ISBN:9781450323055

DOI:10.1145/2541940

General Chairs:
Rajeev Balasubramonian
University of Utah
,
Al Davis
University of Utah
,
Program Chair:
Sarita Adve
University of Illinois at Urbana-Champ

ACM SIGARCH Computer Architecture News Volume 42, Issue 1
ASPLOS '14
March 2014
729 pages
ISSN:0163-5964
DOI:10.1145/2654822
Editor:
Doug DeGroot
acm dot org
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 49, Issue 4
ASPLOS '14
April 2014
729 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/2644865
Editors:
Mark W. Bailey
Hamilton College, Clinton, NY
,
Rajeev Balasubramonian
University of Utah
,
Al Davis
University of Utah
,
Sarita Adve
University of Illinois at Urbana-Champ
Issue’s Table of Contents

Copyright © 2014 ACM.

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Published: 24 February 2014

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Saez JCastro FFanizzi GPrieto-Matias M(2021)LFOC+: A Fair OS-level Cache-Clustering Policy for Commodity Multicore SystemsIEEE Transactions on Computers10.1109/TC.2021.3112970(1-1)Online publication date: 2021
https://doi.org/10.1109/TC.2021.3112970
Bacou MTchana AHagimont D(2019)Your Containers Should be WYSIWYG2019 IEEE International Conference on Services Computing (SCC)10.1109/SCC.2019.00022(56-64)Online publication date: Jul-2019
https://doi.org/10.1109/SCC.2019.00022
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https://doi.org/10.1109/ISPASS.2019.00033
Wang HLuo FIbrahim MKayiran OJog A(2018)Efficient and Fair Multi-programming in GPUs via Effective Bandwidth Management2018 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2018.00030(247-258)Online publication date: Feb-2018
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Feliu JEyerman SSahuquillo JPetit SEeckhout L(2017)Improving IBM POWER8 Performance Through Symbiotic Job SchedulingIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2017.269170828:10(2838-2851)Online publication date: 1-Oct-2017
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Wang QWang JShen LWang Z(2017)A Software-Hardware Co-designed Methodology for Efficient Thread Level Speculation2017 IEEE International Conference on Computer and Information Technology (CIT)10.1109/CIT.2017.49(184-191)Online publication date: Aug-2017
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Tomusk EDubach CO'boyle M(2016)Selecting Heterogeneous Cores for DiversityACM Transactions on Architecture and Code Optimization10.1145/301416513:4(1-25)Online publication date: 16-Dec-2016
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