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An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)

Published: 26 February 2014 Publication History

Abstract

We introduce a new SEU mitigation approach which minimizes the scrubbing effort by a) using an automatic classification of the criticality of netlist instances and their resulting configuration bits, and by b) minimizing the number of frames which must be scrubbed by using intelligent floorplanning. The criticality of configuration bits is defined by the actions needed to correct a radiation-induced SEU at this bit. Indeed, circuits that involve feedback loops might still and infinitely cause a malfunction even if scrubbing is applied to involved configuration frames. Here, only supplementary state-restoring might be a viable solution. By analyzing an FPGA design already at the logic level and partition configuration bits of the resulting FPGA mapping into so-called essential bits and critical bits, we are able to significantly reduce the number of time consuming state-restoring actions. Moreover, by using placement and routing constraints, it is shown how to minimize the number of frames which have to be reconfigured or checked when using scrubbing. By applying both methods, we will show a reduction of the Mean-Time-To-Repair (MTTR) for sequential benchmark circuits by up to 48.5% compared to a state-of-the-art approach.

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  1. An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)

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    cover image ACM Conferences
    FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
    February 2014
    272 pages
    ISBN:9781450326711
    DOI:10.1145/2554688
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 26 February 2014

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    Author Tags

    1. checkpointing
    2. floorplanning
    3. mttr
    4. netlist analysis
    5. scrubbing
    6. seu mitigation

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    Acceptance Rates

    FPGA '14 Paper Acceptance Rate 30 of 110 submissions, 27%;
    Overall Acceptance Rate 125 of 627 submissions, 20%

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