An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)
Abstract
Index Terms
- An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)
Recommendations
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning
Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-...
Combining checkpointing and scrubbing in FPGA-based real-time systems
VTS '13: Proceedings of the 2013 IEEE 31st VLSI Test Symposium (VTS)SRAM-based FPGAs provide an attractive solution for building high-performance embedded computing systems. Fault tolerant mechanisms are usually implemented in FPGA-based critical systems to improve their vulnerability to transient faults. Most fault ...
Fast floorplanning by look-ahead enabled recursive bipartitioning
A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by the ...
Comments
Information & Contributors
Information
Published In
- General Chair:
- Vaughn Betz,
- Program Chair:
- George A. Constantinides
Sponsors
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Check for updates
Author Tags
Qualifiers
- Poster
Conference
Acceptance Rates
Upcoming Conference
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0