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OmpSs@Zynq all-programmable SoC ecosystem

Published: 26 February 2014 Publication History

Abstract

OmpSs is an OpenMP-like directive-based programming model that includes heterogeneous execution (MIC, GPU, SMP, etc.) and runtime task dependencies management. Indeed, OmpSs has largely influenced the recently appeared OpenMP 4.0 specification. Zynq All-Programmable SoC combines the features of a SMP and a FPGA and benefits DLP, ILP and TLP parallelisms in order to efficiently exploit the new technology improvements and chip resource capacities. In this paper, we focus on programmability and heterogeneous execution support, presenting a successful combination of the OmpSs programming model and the Zynq All-Programmable SoC platforms.

References

[1]
Altera, Corp. Nios II C2H Compiler User Guide, 2009.
[2]
E. Ayguade and et. al. A proposal to extend the openmp tasking model for heterogeneous architectures. In Proceedings of the 5th International Workshop on OpenMP: Evolving OpenMP in an Age of Extreme Parallelism, IWOMP '09, pages 154--167. Springer-Verlag, 2009.
[3]
E. Ayguadé and et. al. The Design of OpenMP Tasks. IEEE Trans. Parallel Distrib. Syst., 20(3):404--418, 2009.
[4]
Barcelona Supercomputing Center. Extrae Instrumentation Library, Sept. 2013. http://www.bsc.es/computer-sciences/extrae.
[5]
Barcelona Supercomputing Center. Paraver Visualization Tool, Sept. 2013. http://www.bsc.es/computer-sciences/performance-tools/paraver.
[6]
Barcelona Supercomputing Center. Programming Models @ BSC, Sept. 2013. http://pm.bsc.es/mcxx.
[7]
I. Buck, T. Foley, D. Horn, J. Sugerman, K. Fatahalian, M. Houston, and P. Hanrahan. Brook for GPUs: stream computing on graphics hardware. In SIGGRAPH '04: ACM SIGGRAPH 2004 Papers, pages 777--786, New York, NY, USA, 2004. ACM Press.
[8]
A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J. H. Anderson, S. Brown, and T. Czajkowski. Legup: High-level synthesis for fpga-based processor/accelerator systems. In Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '11, pages 33--36, New York, NY, USA, 2011. ACM.
[9]
R. H. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE Journal of Solid-State Circuits, 9:256--268, Oct. 1974.
[10]
R. Dolbeau, S. Bihan, and F. Bodin. HMPP: A hybrid multi-core parallel programming environment. In First Workshop on General Purpose Processing on Graphics Processing Units, October 2007.
[11]
H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger. Dark silicon and the end of multicore scaling. In Proceedings of the 38th annual international symposium on Computer architecture, ISCA '11, pages 365--376, New York, NY, USA, 2011. ACM.
[12]
R. Hameed and et. al. Understanding sources of inefficiency in general-purpose chips. In Proceedings of the 37th annual international symposium on Computer architecture, ISCA '10, pages 37--47, New York, NY, USA, 2010. ACM.
[13]
Khronos OpenCL Working Group. The OpenCL Specification. Aaftab Munshi, Ed., 2009.
[14]
W. A. Najjar and J. R. Villarreal. Fpga code accelerators - the compiler perspective. In DAC, page 141, 2013.
[15]
Nvidia. CUDA Compute Unified Device Architecture - Programming Guide, 2007.
[16]
OpenMP Architecture Review Board. OpenMP 3.0 Specification. http://www.openmp.org, May 2008.
[17]
A. Papakonstantinou, D. Chen, W.-M. Hwu, J. Cong, and Y. Liang. Throughput-oriented kernel porting onto fpgas. In Proceedings of the 50th Annual Design Automation Conference, DAC '13, pages 11:1--11:10, New York, NY, USA, 2013. ACM.
[18]
D. C. Pham and et. al. Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. Solid-State Circuits, IEEE Journal of, 41(1):179--196, 2006.
[19]
The Portland Group. PGI Accelerator Programming Model for Fortran & C.
[20]
G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, and M. B. Taylor. Conservation cores: reducing the energy of mature computations. volume 38, pages 205--218, New York, NY, USA, Mar. 2010. ACM.
[21]
J. R. Villarreal, A. Park, W. A. Najjar, and R. Halstead. Designing modular hardware accelerators in c with roccc 2.0. In R. Sass and R. Tessier, editors, FCCM, pages 127--134. IEEE Computer Society, 2010.
[22]
Xilinx. Zynq-7000 All Programmable SoC, Sept. 2013. http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/.

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cover image ACM Conferences
FPGA '14: Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
February 2014
272 pages
ISBN:9781450326711
DOI:10.1145/2554688
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 26 February 2014

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Author Tags

  1. automatic hardware generation framework
  2. heterogenous parallel programming model
  3. task dataflow models

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FPGA '14 Paper Acceptance Rate 30 of 110 submissions, 27%;
Overall Acceptance Rate 125 of 627 submissions, 20%

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  • (2021)The AXIOM Project: IoT on Heterogeneous Embedded PlatformsIEEE Design & Test10.1109/MDAT.2019.295233538:5(74-81)Online publication date: Oct-2021
  • (2020)Extending High-Level Synthesis with High-Performance Computing Performance Visualization2020 IEEE International Conference on Cluster Computing (CLUSTER)10.1109/CLUSTER49012.2020.00047(371-380)Online publication date: Sep-2020
  • (2020)OpenMP Device Offloading to FPGAs Using the Nymble InfrastructureOpenMP: Portable Multi-Level Parallelism on Modern Systems10.1007/978-3-030-58144-2_17(265-279)Online publication date: 1-Sep-2020
  • (2019)OpenMP on FPGAs—A SurveyOpenMP: Conquering the Full Hardware Spectrum10.1007/978-3-030-28596-8_7(94-108)Online publication date: 9-Aug-2019
  • (2018)An FPGA target for the StarPU heterogeneous runtime system2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449373(1-8)Online publication date: Jul-2018
  • (2018)Trade-Off of Offloading to FPGA in OpenMP Task-Based ProgrammingEvolving OpenMP for Evolving Architectures10.1007/978-3-319-98521-3_7(96-110)Online publication date: 29-Aug-2018
  • (2017)HGum: Messaging framework for hardware accelerators2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2017.8279799(1-8)Online publication date: Dec-2017
  • (2017)Monitoring Heterogeneous Applications with the OpenMP Tools InterfaceTools for High Performance Computing 201610.1007/978-3-319-56702-0_3(41-57)Online publication date: 9-May-2017
  • (2016)Exploring dataflow-based thread level parallelism in cyber-physical systemsProceedings of the ACM International Conference on Computing Frontiers10.1145/2903150.2906829(295-300)Online publication date: 16-May-2016
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