research-article

A study on unroutable placement recognition

Authors:

Ting-Chi WangAuthors Info & Claims

ISPD '14: Proceedings of the 2014 on International symposium on physical design

Pages 19 - 26

https://doi.org/10.1145/2560519.2560522

Published: 30 March 2014 Publication History

Abstract

To avoid producing unroutable placement solutions, many state-of-the-art routability-driven placers iteratively invoke global routers to evaluate their placement solutions and then perform routability optimization. However, using a global router to evaluate hard-to-route placement solutions may spend considerable runtime and it cannot guarantee that a placement is truly unroutable to any router. This paper presents an unroutable placement recognizer based on a window-based layout scanning algorithm, which can confirm some placements that are exactly unroutable among a set of hard-to-route placements. In addition, if a placement is recognized to be unroutable, the recognizer can point out unroutable regions and report a lower bound of total overflow for the placement. The experimental results reveal that the proposed recognizer can find out 16 placements that are definitely unroutable among 23 widely used hard-to-route global routing benchmarks.

References

[1]

ISPD 2008 Global Routing Contest and Benchmark Suite. Available: http://archive.sigda.org/ispd2008/contests/ispd08rc.html

[2]

M. D. Moffitt and C. N. Sze, "Wire synthesizable global routing for timing closure," in Proc. ASP-DAC, pp. 545--550, 2011.

Digital Library

[3]

J. Hu et al, "Completing high-quality global routes," in Proc. ICCAD, pp. 35--41, 2010.

Digital Library

[4]

H.-Y. Chen et al. "High-performance global routing with fast overflow reduction." in Proc. ASP-DAC, pp. 582--587, 2009.

Digital Library

[5]

Y. Xu and C. Chu, "MGR: Multi-level global router," in Proc. ICCAD, pp.250--255, 2011.

Digital Library

[6]

Y.-J. Chang et al, "NTHU-Route 2.0: a fast and stable global router," in Proc. ICCAD, pp. 338--343, 2008.

Digital Library

[7]

T.-H. Wu et al., "GRIP: Scalable 3-D global routing using integer programming," in Proc. DAC, pp. 320--325, 2009.

Digital Library

[8]

Y.-J. Chang et al., "GLADE: A modern global router considering layer directives," in Proc. ICCAD, pp.319--323, 2010.

Digital Library

[9]

W.-H. Liu et al., "NCTU-GR 2.0: multithreaded collision-aware global routing with bounded-length maze routing," IEEE TCAD, 32(5), pp. 709--722, 2013.

Digital Library

[10]

K.-R. Dai et al., "NCTU-GR: efficient simulated evolution-based rerouting and congestion-relaxed layer assignment on 3-D global routing," IEEE TVLSI, 20(3), pp. 459--472, 2012.

Digital Library

[11]

N. Viswanathan et al., "The ISPD-2011 routability-driven placement contest and benchmark suite," in Proc. ISPD, pp. 141--146, 2011.

Digital Library

[12]

H. Shojaei et al., "Congestion analysis for global routing via integer programming," in Proc. ICCAD, pp. 256--262, 2011.

Digital Library

[13]

W.-H. Liu et al., "A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing," in Proc. ICCAD, pp. 713--719, 2012.

Digital Library

[14]

X. He et al., "Ripple: an effective routability-driven placer by iterative cell movement", in Proc. ICCAD, pp. 74--79, 2011.

Digital Library

[15]

M.-C. Kim et al., "A SimPLR method for routability-driven placement," in Proc. ICCAD, pp. 80--84, 2011.

Digital Library

[16]

J. Hu et al., "Taming the complexity of coordinated place and route," in Proc. DAC, 2013.

Digital Library

[17]

X. He et al., "Ripple 2.0: High quality routability-driven placement via global router integration," in Proc. DAC, 2013.

Digital Library

[18]

W.-H. Liu et al., "Optimization of placement solutions for routability," in Proc. DAC, 2013.

Digital Library

[19]

M. R. Garey and D. S. Johnson, "Computers and intractability: a guide to the theory of NP-Completeness," New York: W. H. Freeman, 1983.

Digital Library

[20]

W.-H. Liu et al., "Routing congestion estimation with real design constraints," in Proc. DAC, No. 92, 2013.

Digital Library

[21]

M.-K. Hsu et al., "Routability-driven analytical placement for mixed-size circuit designs", in Proc. ICCAD, pp. 80--84, 2011.

Digital Library

[22]

Jason Cong et al., "Optimizing routability in large-scale mixed-size placement," in Proc. ASP-DAC, pp.441--446, 2013.

Cited By

Chan WHo PKahng ASaxena POzdal MChu C(2017)Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine LearningProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036681(15-21)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036681
Chan WDu YKahng ANath SSamadi K(2016)BEOL stack-aware routability prediction from placement using data mining techniques2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753259(41-48)Online publication date: Oct-2016
https://doi.org/10.1109/ICCD.2016.7753259
Bustany IChinnery DShinnerl JYutsis VDavoodi AYoung E(2015)ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven PlacementProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2723572(157-164)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2723572

Index Terms

A study on unroutable placement recognition
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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cover image ACM Conferences

ISPD '14: Proceedings of the 2014 on International symposium on physical design

March 2014

180 pages

ISBN:9781450325929

DOI:10.1145/2560519

General Chair:
Cliff Sze
IBM Research
,
Program Chair:
Azadeh Davoodi
University of Wisconsin - Madison

Copyright © 2014 ACM.

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 March 2014

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National Science Council Taiwan

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ISPD'14

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SIGDA

ISPD'14: International Symposium on Physical Design

March 30 - April 2, 2014

California, Petaluma, USA

Acceptance Rates

ISPD '14 Paper Acceptance Rate 14 of 40 submissions, 35%;

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Cited By

Chan WHo PKahng ASaxena POzdal MChu C(2017)Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine LearningProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036681(15-21)Online publication date: 19-Mar-2017
https://dl.acm.org/doi/10.1145/3036669.3036681
Chan WDu YKahng ANath SSamadi K(2016)BEOL stack-aware routability prediction from placement using data mining techniques2016 IEEE 34th International Conference on Computer Design (ICCD)10.1109/ICCD.2016.7753259(41-48)Online publication date: Oct-2016
https://doi.org/10.1109/ICCD.2016.7753259
Bustany IChinnery DShinnerl JYutsis VDavoodi AYoung E(2015)ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven PlacementProceedings of the 2015 Symposium on International Symposium on Physical Design10.1145/2717764.2723572(157-164)Online publication date: 29-Mar-2015
https://dl.acm.org/doi/10.1145/2717764.2723572

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