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Clock tree resynthesis for multi-corner multi-mode timing closure

Published: 30 March 2014 Publication History

Abstract

With aggressive technology scaling and complex design scenarios, timing closure has become a challenging and tedious job for the designers. Timing violations persist for multi- corner, multi-mode designs in the deep-routing stage although careful optimization has been applied at every step after synthesis. Useful clock skew optimization has been suggested as an effective way to achieve design convergence and timing closure. Existing approaches on useful skew optimization (i) calculate clock skew at sequential elements before the actual tree is synthesized, and (ii) do not account for the implementability of the calculated schedules at the later stages of design cycle. Our approach is based on a skew scheduling engine which works on an already built clock tree. The output of the engine is a set of positive and negative offsets which translate to the delay and accelerations respectively in clock arrival at the clock tree pins. A novel algorithm is presented to accurately realize these offsets in the clock tree. Experimental results on large-scale industrial designs demonstrate that our approach achieves respectively 57%, 12% and 42% average improvement in total negative slack (TNS), worst negative slack (WNS) and failure-end-point (FEP) with an average overhead of 26% in clock tree area.

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  • (2024)CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor SizingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332859232:1(137-149)Online publication date: Jan-2024
  • (2021)An Approximate Symmetry Clock Tree Design with Routing Topology Prediction2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS47672.2021.9531772(92-96)Online publication date: 9-Aug-2021
  • (2019)Scalable Construction of Clock Trees With Useful Skew and High Timing QualityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443738:6(1161-1174)Online publication date: 1-Jun-2019
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      cover image ACM Conferences
      ISPD '14: Proceedings of the 2014 on International symposium on physical design
      March 2014
      180 pages
      ISBN:9781450325929
      DOI:10.1145/2560519
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      Published: 30 March 2014

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      Author Tags

      1. clock tree optimization
      2. clock tree synthesis
      3. timing closure

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      March 30 - April 2, 2014
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      View all
      • (2024)CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor SizingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.332859232:1(137-149)Online publication date: Jan-2024
      • (2021)An Approximate Symmetry Clock Tree Design with Routing Topology Prediction2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS47672.2021.9531772(92-96)Online publication date: 9-Aug-2021
      • (2019)Scalable Construction of Clock Trees With Useful Skew and High Timing QualityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443738:6(1161-1174)Online publication date: 1-Jun-2019
      • (2018)TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew ViolationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265222137:1(231-244)Online publication date: Jan-2018
      • (2017)A Clock Tree Optimization Framework with Predictable Timing QualityProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062184(1-6)Online publication date: 18-Jun-2017
      • (2017)Clock Tree Construction based on Arrival Time ConstraintsProceedings of the 2017 ACM on International Symposium on Physical Design10.1145/3036669.3036671(67-74)Online publication date: 19-Mar-2017
      • (2016)An Efficient Approach Targeting Broken Topological Clock Path for Master — Generated Clock Pair2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)10.1109/iNIS.2016.034(102-107)Online publication date: Dec-2016
      • (2016)An effective and efficient algorithm to analyse and debug clock propagation issues2016 20th International Symposium on VLSI Design and Test (VDAT)10.1109/ISVDAT.2016.8064849(1-6)Online publication date: May-2016
      • (2016)MCMM clock tree optimization based on slack redistribution using a reduced slack graph2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428039(366-371)Online publication date: Jan-2016
      • (2015)TILAProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840835(110-117)Online publication date: 2-Nov-2015
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