research-article

Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs

Authors:

Shreepad Panth,

Kambiz Samadi,

Yang Du,

Sung Kyu LimAuthors Info & Claims

ISPD '14: Proceedings of the 2014 on International symposium on physical design

Pages 47 - 54

https://doi.org/10.1145/2560519.2560531

Published: 30 March 2014 Publication History

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Abstract

Monolithic 3D is an emerging technology that enables integration density which is orders of magnitude higher than that offered by through-silicon-vias (TSV). In this paper we demonstrate that a modified 2D placement technique, coupled with a post-placement partitioning step, is sufficient to produce high quality monolithic 3D placement solutions. We also present a commercial router based monolithic inter-tier via (MIV) insertion methodology that dramatically improves the routability of monolithic 3D-ICs. We develop a routing demand model for monolithic 3D-ICs, and use it to develop an O(N) min-overflow partitioner that enhances routability by off-loading demand from one tier to another. This technique reduces the routed wirelength and the power delay product (PDP) by up to 4% and 4.33% respectively, under the same half-perimeter wirelength. This allows a two-tier monolithic 3D-IC to achieve, on average, 19.2% and 12.1% improvement in routed wirelength and PDP over 2D, even with reduced metal layer usage.

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Cited By

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Zhao XLi WZeng ZHuang ZXie BLi XBao YNakamura YWang Y(2025)Toward Advancing 3D-ICs Physical Design: Challenges and OpportunitiesProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3703135(294-301)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3703135
Park SPark H(2024)Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration2024 International Conference on Electronics, Information, and Communication (ICEIC)10.1109/ICEIC61013.2024.10457092(1-4)Online publication date: 28-Jan-2024
https://doi.org/10.1109/ICEIC61013.2024.10457092
Zhao XChen SQiu YLi JHuang ZXie BLi XBao Y(2023)iPL-3D: A Novel Bilevel Programming Model for Die-to-Die Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323811(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323811
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Index Terms

Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

ISPD '14: Proceedings of the 2014 on International symposium on physical design

March 2014

180 pages

ISBN:9781450325929

DOI:10.1145/2560519

General Chair:
Cliff Sze
IBM Research
,
Program Chair:
Azadeh Davoodi
University of Wisconsin - Madison

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 March 2014

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Qualcomm

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ISPD'14

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SIGDA

ISPD'14: International Symposium on Physical Design

March 30 - April 2, 2014

California, Petaluma, USA

Acceptance Rates

ISPD '14 Paper Acceptance Rate 14 of 40 submissions, 35%;

Overall Acceptance Rate 62 of 172 submissions, 36%

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International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

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Cited By

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Zhao XLi WZeng ZHuang ZXie BLi XBao YNakamura YWang Y(2025)Toward Advancing 3D-ICs Physical Design: Challenges and OpportunitiesProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3703135(294-301)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3703135
Park SPark H(2024)Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration2024 International Conference on Electronics, Information, and Communication (ICEIC)10.1109/ICEIC61013.2024.10457092(1-4)Online publication date: 28-Jan-2024
https://doi.org/10.1109/ICEIC61013.2024.10457092
Zhao XChen SQiu YLi JHuang ZXie BLi XBao Y(2023)iPL-3D: A Novel Bilevel Programming Model for Die-to-Die Placement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323811(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323811
Ku BChang KLim S(2020)Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.295254239:6(1151-1164)Online publication date: Jun-2020
https://doi.org/10.1109/TCAD.2019.2952542
Sketopoulos NSotiriou CPavlidis V(2020)Metal Stack and Partitioning Exploration for Monolithic 3D ICs2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI49217.2020.00079(398-403)Online publication date: Jul-2020
https://doi.org/10.1109/ISVLSI49217.2020.00079
Sketopoulos NSotiriou CSamaras VHomayoun HTaskin BMohsenin TZhao W(2019)Investigation and Trade-offs in 3DIC Partitioning MethodologiesProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3319487(451-455)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3319487
Lin SKim D(2019)Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits20th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2019.8697450(329-334)Online publication date: Mar-2019
https://doi.org/10.1109/ISQED.2019.8697450
Vivet PThuries SBilloint OChoisnet SLattard DBeigne EBatude P(2018)Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS.2018.8617955(157-160)Online publication date: Dec-2018
https://doi.org/10.1109/ICECS.2018.8617955
Lin JYang J(2017)Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.269590036:11(1856-1868)Online publication date: Nov-2017
https://doi.org/10.1109/TCAD.2017.2695900
Samal SSamadi KKamal PDu YLim S(2017)Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.261637736:6(992-1003)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2616377
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TSV-aware analytical placement for 3D IC designs