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TAU 2014 contest on removing common path pessimism during timing analysis

Published: 30 March 2014 Publication History

Abstract

To margin against modeling limitations in considering design and electrical complexities (e.g., crosstalk coupling, voltage drops) as well as variability (e.g., manufacturing process, environmental), "early" and "late" signal propagation delays in static timing analysis are often made pessimistic by addition of extra guard bands. While these forced "early-late splits" provide desired margins, the splits applied across the entire design introduce excessive and undesired pessimism. To this end, "common path pessimism removal (CPPR)" eliminates the redundant pessimism during timing analysis.
The aim of the TAU 2014 timing contest is to seek novel ideas for fast CPPR by: (i) introducing the concept and importance of common path pessimism removal while highlighting the exponential run-time complexity of an optimal solution, (ii) encouraging novel parallelization techniques (including multi-threading), and (iii) facilitating the creation of a timing analysis and CPPR framework with benchmarks to further advance research in this area.

References

[1]
J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach, Springer, 2009.
[2]
D. Sinha, L. Guerra e Silva, J. Wang, S. Raghunathan, D. Netrabile and A. Shebaita, "TAU 2013 variation aware timing analysis contest", Proc. International Symposium on Physical Design, 2013, pp. 171--178.

Cited By

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  • (2024)Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.336140143:7(2151-2162)Online publication date: Jul-2024
  • (2023)Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328626142:12(4973-4984)Online publication date: Dec-2023
  • (2022)A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312475841:10(3466-3478)Online publication date: Oct-2022
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    cover image ACM Conferences
    ISPD '14: Proceedings of the 2014 on International symposium on physical design
    March 2014
    180 pages
    ISBN:9781450325929
    DOI:10.1145/2560519
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    Publication History

    Published: 30 March 2014

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    Author Tags

    1. algorithms
    2. common path pessimism removal
    3. design
    4. experimentation
    5. performance
    6. timing analysis

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    March 30 - April 2, 2014
    California, Petaluma, USA

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    ISPD '14 Paper Acceptance Rate 14 of 40 submissions, 35%;
    Overall Acceptance Rate 62 of 172 submissions, 36%

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    Cited By

    View all
    • (2024)Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.336140143:7(2151-2162)Online publication date: Jul-2024
    • (2023)Accelerating Static Timing Analysis Using CPU–GPU Heterogeneous ParallelismIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328626142:12(4973-4984)Online publication date: Dec-2023
    • (2022)A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312475841:10(3466-3478)Online publication date: Oct-2022
    • (2022)Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various GatesIEEE Transactions on Applied Superconductivity10.1109/TASC.2022.316105232:5(1-9)Online publication date: Aug-2022
    • (2022)Efficient Critical Paths Search Algorithm using Mergeable Heap2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712566(190-195)Online publication date: 17-Jan-2022
    • (2021)HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643457(1-9)Online publication date: 1-Nov-2021
    • (2021)A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586085(715-720)Online publication date: 5-Dec-2021
    • (2016)Statistical path tracing in timing graphsProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2898096(1-6)Online publication date: 5-Jun-2016
    • (2016)UI-Timer 1.0IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.252456635:11(1862-1875)Online publication date: 1-Nov-2016
    • (2016)A fast and accurate approach for common path pessimism removal in static timing analysis2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7539131(2623-2626)Online publication date: May-2016
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