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ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement

Published: 30 March 2014 Publication History

Abstract

The public release of realistic industrial placement benchmarks by IBM and Intel Corporations from 1998--2013 has been crucial to the progress in physical-design algorithms during those years. Direct comparisons of academic tools on these test cases, including widely publicized contests, have spurred researchers to discover faster, more scalable algorithms with significantly improved quality of results.
Nevertheless, close examination of these benchmarks reveals that the removal of important physical data from them prior to release now presents a serious obstacle to any accurate appraisal of the detailed routability of their placements. Recent studies suggest that academic placement algorithms may lack sufficient awareness of the pin geometry and routing rules missing from these benchmarks to adequately address the challenge of computing routable placements at 28nm-process technologies and below.
In this article, the reconstitution of the existing benchmarks via the injection of realistic yet fictitious pin data and routing rules is described. The enhanced benchmarks enable more meaningful comparisons of new placement algorithms by industrial detailed routing, beginning with the 2014 ISPD placement contest.

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      cover image ACM Conferences
      ISPD '14: Proceedings of the 2014 on International symposium on physical design
      March 2014
      180 pages
      ISBN:9781450325929
      DOI:10.1145/2560519
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 30 March 2014

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      Author Tags

      1. detailed routing
      2. global routing
      3. placement
      4. placement evaluation
      5. routability

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      ISPD'14
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      ISPD'14: International Symposium on Physical Design
      March 30 - April 2, 2014
      California, Petaluma, USA

      Acceptance Rates

      ISPD '14 Paper Acceptance Rate 14 of 40 submissions, 35%;
      Overall Acceptance Rate 62 of 172 submissions, 36%

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      ISPD '25
      International Symposium on Physical Design
      March 16 - 19, 2025
      Austin , TX , USA

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      Cited By

      View all
      • (2024)Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID60093.2024.00056(300-305)Online publication date: 6-Jan-2024
      • (2024)Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary ConditionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336366632:5(810-822)Online publication date: May-2024
      • (2024)Machine learning optimal ordering in global routing problems in semiconductorsScientific Reports10.1038/s41598-024-82226-914:1Online publication date: 28-Dec-2024
      • (2023)Progress of Placement Optimization for Accelerating VLSI Physical DesignElectronics10.3390/electronics1202033712:2(337)Online publication date: 9-Jan-2023
      • (2023)DRC Violation Prediction After Global Route Through Convolutional Neural NetworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327193231:9(1425-1438)Online publication date: Sep-2023
      • (2023)Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319481642:4(1255-1267)Online publication date: Apr-2023
      • (2022)OPDB: A Scalable and Modular Design BenchmarkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309679441:6(1878-1887)Online publication date: Jun-2022
      • (2022)Pin-Accessible Legalization for Mixed-Cell-Height CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.305322341:1(143-154)Online publication date: Jan-2022
      • (2021)OptiPlace: optimized placement solution for mixed-size designsAnalog Integrated Circuits and Signal Processing10.1007/s10470-021-01864-5Online publication date: 13-May-2021
      • (2019)RePlAce: Advancing Solution Quality and Routability Validation in Global PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285922038:9(1717-1730)Online publication date: Sep-2019
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