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A new DRAM architecture and its control method for the system power consumption

Published: 20 May 2014 Publication History

Abstract

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a re-write operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. According to a new proposed method the refresh operation frequency and its power consumption reduce to 1/(2 to the Nth) (N=1, 2, 3, 4) when full memory capacity is not required, by effectively extending the refresh operation interval. The proposal includes the conversion from 1 cell/bit to (2 to the Nth) cells/bit, which reduces the variation of retention times among memory cells. This leads the refresh operation frequency from 1/(2 to the Nth) to 1/(2 to the Nth) X 1/(2 to the Nth), while it accompanies the additional charging power for the composed memory cell. A system can select the best way of 1 cell/bit and (2 to the Nth) cells/bit from the total viewpoint, while all conventional functions and operations in the full array access mode are fully compatible.

References

[1]
N. C. C. Lu and H. H. Chao, "Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs," IEEE Journal of Solid-State Circuits, vol.SC-19, No.4, pp.451--454, Aug. 1984.
[2]
Y. Riho, K. Nakazato, "A New Extension Method of Retention Time for Memory Cell on Dynamic Random Access Memory," GLSVLSI2013 Conf., May 2013.
[3]
Y. Riho, K. Nakazato, "Partial Access Mode: A New Method for Reducing Power Consumption of Dynamic Random Access Memory" IEEE trans. on TVLSI Systems, Published, 2013.
[4]
T. Ohsawa, K. Kai, K. Murakami, "Optimizing the DRAM Refresh Count for Merged DRAM/Logic LSIs" ISLPED1998 Conf., 1998.
[5]
J. Liu, B. Jaiyen, R. Veras, O. Mutlu, "RAIDR: Retention-Aware Intelligent DRAM Refresh" ISCA2012 Conf., 2012.
[6]
R. K. Venkatesan, S. Herr, E. Rotenberg, "Retention-Aware Placement in DRAM (RAPID): Software Methods for Quasi-Non-Volatile DRAM" HPCA2012 Conf., 2012.
[7]
J. Liu, B. Jaiyen, R. Veras, O. Mutlu, "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms" ISCA2013 Conf., 2013.

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  1. A new DRAM architecture and its control method for the system power consumption

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    cover image ACM Conferences
    GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI
    May 2014
    376 pages
    ISBN:9781450328166
    DOI:10.1145/2591513
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 20 May 2014

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    Author Tags

    1. composed memory cell
    2. partial access mode 0/1/2 (pam0/1/2)
    3. self refresh (SELF)

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    May 21 - 23, 2014
    Texas, Houston, USA

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    GLSVLSI '14 Paper Acceptance Rate 49 of 179 submissions, 27%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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