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System-level reliability exploration framework for heterogeneous MPSoC

Published: 20 May 2014 Publication History

Abstract

Power density of digital circuits increased at alarming rate for deep sub-micron CMOS technology, turning reliability into a serious design concern. On the other hand, ever-growing task complexity with strict performance budget forced designers to adopt complex, heterogeneous MPSoCs as the implementation choice. Several commercial system-level design platforms exist currently for design, exploration and implementation of MPSoC. In this paper, we propose a system-level reliability exploration framework by extending a commercial system-level design flow. Using this framework, a heterogeneous MPSoC is designed which can accept a custom mapping algorithm based on the MPSoC topology before the actual task deployment. The dynamic reliability-aware task management is able to consider the desired reliability constraints of tasks as well as reliability levels of the system components. We report our experimental findings using state-of-the-art benchmark applications.

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Cited By

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  • (2018)A Thermal Balance Oriented Task Mapping for CMPsProceedings of the 8th International Conference on Information Communication and Management10.1145/3268891.3268902(12-16)Online publication date: 22-Aug-2018
  • (2015)A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core SystemsProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2800992(1-7)Online publication date: 31-Aug-2015
  • (2015)Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliabilitySixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085457(392-396)Online publication date: Mar-2015

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      cover image ACM Conferences
      GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI
      May 2014
      376 pages
      ISBN:9781450328166
      DOI:10.1145/2591513
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 20 May 2014

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      Author Tags

      1. reliability exploration
      2. system-level design
      3. task mapping

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      Cited By

      View all
      • (2018)A Thermal Balance Oriented Task Mapping for CMPsProceedings of the 8th International Conference on Information Communication and Management10.1145/3268891.3268902(12-16)Online publication date: 22-Aug-2018
      • (2015)A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core SystemsProceedings of the 28th Symposium on Integrated Circuits and Systems Design10.1145/2800986.2800992(1-7)Online publication date: 31-Aug-2015
      • (2015)Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliabilitySixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085457(392-396)Online publication date: Mar-2015

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