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Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis

Published: 20 May 2014 Publication History

Abstract

The correct functionality of quasi-delay-insensitive asynchronous circuits can be jeopardized by the presence and propagation of transient faults. If these faults are latched, they will corrupt data validity and can make the whole circuit to stall, given the strict event ordering constraints imposed by handshaking protocols. This is particularly concerning for the delay-insensitive minterm synthesis logic style, widely adopted by asynchronous designers to implement combinatory quasi-delay-insensitive logic, because it makes extensive use of C-elements and these components are rather vulnerable to transient effects. This paper demonstrates that this logic style submits C-elements to their most vulnerable states during operation. It accordingly proposes the alternative use of the delay-insensitive maxterm synthesis for hardening QDI circuits against transient faults. The latter is a logic style based on the return-to-one 4-phase protocol. Although this style also relies on extensive usage of C-elements, the states where these components are most vulnerable are avoided. Results display improvements of over 300% in C-elements tolerance to transient faults, in the best case.

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Cited By

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  • (2019)Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2019.00023(114-123)Online publication date: May-2019
  • (2018)NCL Synthesis With Conventional EDA Tools: Technology Mapping and OptimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.277220665:6(1981-1993)Online publication date: Jun-2018
  • (2017)A comparison of quasi-delay-insensitive asynchronous adder designs corresponding to return-to-zero and return-to-one handshaking2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053142(1192-1195)Online publication date: Aug-2017
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  1. Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis

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      cover image ACM Conferences
      GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI
      May 2014
      376 pages
      ISBN:9781450328166
      DOI:10.1145/2591513
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 20 May 2014

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      Author Tags

      1. delay-insensitive maxterm synthesis
      2. quasi-delay-insensitive
      3. return-to-one
      4. robustness
      5. transient faults

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      May 21 - 23, 2014
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      Cited By

      View all
      • (2019)Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC.2019.00023(114-123)Online publication date: May-2019
      • (2018)NCL Synthesis With Conventional EDA Tools: Technology Mapping and OptimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2017.277220665:6(1981-1993)Online publication date: Jun-2018
      • (2017)A comparison of quasi-delay-insensitive asynchronous adder designs corresponding to return-to-zero and return-to-one handshaking2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2017.8053142(1192-1195)Online publication date: Aug-2017
      • (2014)Advances on the state of the art in QDI design2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC.2014.7004169(163-164)Online publication date: Oct-2014

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