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A performance enhancing hybrid locally mesh globally star NoC topology

Published: 20 May 2014 Publication History

Abstract

With the rapid increase in the chip density, Network-on-Chip (NoC) is becoming the prevalent architecture for today's complex chip multi processor (CMP) based systems. One of the major challenges of the NoC is to design an enhanced parallel communication centric scalable architecture for the on chip communication. In this paper, a hybrid Mesh based Star topology has been proposed to provide low latency, high throughput and more evenly distributed traffic throughout the network. Simulation results show that a maximum of 62% latency benefit (for size 8x8), 55% (for size 8x8), and 42% (for size 12x12) throughput benefits can be achieved for proposed topology over mesh with a small area overhead.

References

[1]
The Network Simulator-NS-2. Online. Available: http://www.isi.edu/nsnam/ns/.
[2]
K.-J. Chen, C.-H. Peng, and F. Lai. Star-type architecture with low transmission latency for a 2D mesh NOC. In IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pages 919--922, 2010.
[3]
P. Ghosal and T. S. Das. L2STAR: A Star Type level-2 2D Mesh architecture for NoC. In Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pages 155--159, 2012.
[4]
P. Ghosal and T. S. Das. Network-on-chip routing using Structural Diametrical 2D mesh architecture. In Third International Conference on Emerging Applications of Information Technology (EAIT), pages 471--474, 2012.
[5]
Z. Song, G. Ma, and D. Song. Hierarchical Star: An Optimal NoC Topology for High-Performance SoC Design. In International Multisymposiums on Computer and Computational Sciences (IMSCCS '08), pages 158--163, 2008.
[6]
S. Suboh, M. Bakhouya, J. Gaber, and T. El-Ghazawi. Analytical modeling and evaluation of network-on-chip architectures. In International Conference on High Performance Computing and Simulation (HPCS), pages 615--622, 2010.
[7]
X. Wang and L. Bandi. A low-area and low-latency network on chip. In 23rd Canadian Conference on Electrical and Computer Engineering (CCECE), pages 1--5, 2010.

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  1. A performance enhancing hybrid locally mesh globally star NoC topology

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    cover image ACM Conferences
    GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI
    May 2014
    376 pages
    ISBN:9781450328166
    DOI:10.1145/2591513
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    Publication History

    Published: 20 May 2014

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    Author Tags

    1. latency
    2. load balancing
    3. noc topology
    4. performance.
    5. throughput

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    GLSVLSI '14: Great Lakes Symposium on VLSI 2014
    May 21 - 23, 2014
    Texas, Houston, USA

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    GLSVLSI '14 Paper Acceptance Rate 49 of 179 submissions, 27%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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