Fabio Pereira
ABSTRACT
This paper presents a resource optimized hardware solution to perform the H.264 8x8 inverse transform. Row/column decomposition is used, arithmetic units are re-used and the transpose memory is replaced by a shift register. The architecture is able to perform 8x8 integer transform calculation in 144 cycles with as few as 431 LUTs on a Xilinx virtex 6 FPGA for 16-bit resolution. To enable the module to process all inverse transforms in H.264, the number of LUTs is increased to 681. When used to calculate all transforms for H.264 videos, the design supports resolutions up to 1280x720@30fps when running at 84 MHz.
- ITU--T. 2005. Recommendation H.264 & ISO/TEC 14496--10 AVC, Advanced Video Coding for Generic Audiovisual Services, 2005 version 3Google Scholar
- - Y. C. Chao, H. H. Tsai, Y. H. Lin, J. F. Yang, and B. D. Liu. 2007. A novel design for computation of all transforms in H.264/AVC decoders. in IEEE Int. Conf. Multimedia Expo, pp. 1914--1917 (Jul 2007)Google Scholar
- J. S. Park, T. Ogunfunmi. 2009. A New Hardware Implementation of the H.264 8x8 Transform and Quantization. 2009 in Acoustics, Speech and Signal Processing, IEEE International Conference on. (2009) Google ScholarDigital Library
Index Terms
- H.264 8x8 inverse transform architecture optimization
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