research-article

A study on the use of parallel wiring techniques for sub-20nm designs

Authors:

Cheng-Kok KohAuthors Info & Claims

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

Pages 129 - 134

https://doi.org/10.1145/2591513.2591588

Published: 20 May 2014 Publication History

Abstract

Wire sizing can be used to reduce the delays of critical nets. However, because of the forbidden pitch issue in sub-20nm designs, wide wires may no longer be an attractive solution because of the restrictive wire spacing requirement from advanced lithography. In this work, we investigate the suitability of the parallel wiring technique, in which multiple parallel wires are used to route the same net, as an alternative to routing a net using a single wide wire. In particular, we study the trade offs between parasitics, timing, power, and routing resources. Our study reveals that wire sizing using both parallel wires and wide wires can be advantageous. Moreover, if high layout densities are required, parallel wiring can be a viable approach in solving timing problems for sub-20nm designs.

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Cited By

Lu RZhang WJiang LLiu G(2023)Slew-Driven Layer Assignment for Advanced Non-default-rule WiresWeb Information Systems and Applications10.1007/978-981-99-6222-8_45(539-550)Online publication date: 9-Sep-2023
https://doi.org/10.1007/978-981-99-6222-8_45
Jiang LLi ZBao CLiu GHuang XLiu WWang T(2022)LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC54400.2022.9939586(1-6)Online publication date: 3-Oct-2022
https://doi.org/10.1109/VLSI-SoC54400.2022.9939586
Liu GZhang XGuo WHuang XLiu WChao KWang T(2022)Timing-Aware Layer Assignment for Advanced Process Technologies Considering via PillarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310029641:6(1957-1970)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3100296
Show More Cited By

Index Terms

A study on the use of parallel wiring techniques for sub-20nm designs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

GLSVLSI '14: Proceedings of the 24th edition of the great lakes symposium on VLSI

May 2014

376 pages

ISBN:9781450328166

DOI:10.1145/2591513

General Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Inst., USA
,
Program Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 May 2014

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GLSVLSI '14: Great Lakes Symposium on VLSI 2014

May 21 - 23, 2014

Texas, Houston, USA

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GLSVLSI '14 Paper Acceptance Rate 49 of 179 submissions, 27%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Lu RZhang WJiang LLiu G(2023)Slew-Driven Layer Assignment for Advanced Non-default-rule WiresWeb Information Systems and Applications10.1007/978-981-99-6222-8_45(539-550)Online publication date: 9-Sep-2023
https://doi.org/10.1007/978-981-99-6222-8_45
Jiang LLi ZBao CLiu GHuang XLiu WWang T(2022)LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC54400.2022.9939586(1-6)Online publication date: 3-Oct-2022
https://doi.org/10.1109/VLSI-SoC54400.2022.9939586
Liu GZhang XGuo WHuang XLiu WChao KWang T(2022)Timing-Aware Layer Assignment for Advanced Process Technologies Considering via PillarsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310029641:6(1957-1970)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3100296
Zhang XZhuang ZLiu GHuang XLiu WGuo WWang TDi Natale GFummi F(2020)MiniDelayProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408484(586-591)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.5555/3408352.3408484
Zhang XZhuang ZLiu GHuang XLiu WGuo WWang T(2020)MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116269(586-591)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116269
Lerner STaskin B(2017)WT-CTS: Incremental Delay Balancing Using Parallel Wiring Type For CTS2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.87(465-470)Online publication date: Jul-2017
https://doi.org/10.1109/ISVLSI.2017.87
Han SLiu WEwetz RKoh CChao KWang T(2017)Delay-driven layer assignment for advanced technology nodes2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858365(456-462)Online publication date: Jan-2017
https://doi.org/10.1109/ASPDAC.2017.7858365

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