Author retrospective for code scheduling and register allocation in large basic blocks

In 1987 we were working at the University of Wisconsin-Madison with Jim Smith, J. T. Hsieh, Koujuch Liou and Andrew Pleszkun on PIPE [4], an unorthodox 'decoupled access-execute processor.' The driving innovation of PIPE was the separation of instructions dealing with memory through a separate and independent instruction stream racing ahead, initiating load and store instructions in-order, synchronized only with other instructions through architectural queues. The queues eliminated the need for allocating and managing temporary registers.

While the problems of register allocation and instruction scheduling were traditionally treated independently, the genesis of this paper came while developing an optimizing compiler for PIPE, with the insight that in a conventional architecture these two closely related problems have conflicting goals that could be played off against each other to maximize benefit: Code scheduling uses as many temporary registers as possible to achieve a higher level of instruction-level parallelism (ILP), while register allocation minimizes the use of temporary registers so that more data items could be allocated to the available registers. As we gained more experience in optimizing for parallel programs, we came to understand that such conflicting goals were commonplace in the trade-off between parallelism and locality [2].

This work introduced the concept of the DAG-driven register allocation. We defined two terms, width and height of a DAG, in the context of code scheduling. The width of a DAG is the maximal number of mutually independent nodes requiring a destination (i.e. target) register and the height of a DAG is the length of its critical path. The shape of the DAG can be changed due to register allocation. For example, while the width can be reduced by reusing registers, the height could be increased. The purpose of DAG-driven register allocation is to minimize the height while keeping the width smaller than the number of available registers.