Kuan-Hsien Ho
ABSTRACT
Asynchronous circuits are a promising design style for low-power and high-performance applications, where asynchronous templates have been widely used to automate the design of asynchronous circuits to reduce design efforts such as the implementation of handshaking mechanisms. Among the templates, pipeline templates are popular in high-performance systems. This paper presents an asynchronous template that can generate pipelines with low glitch-power consumption under the two-phase bundled-data protocol. Moreover, operations of our pipeline template can be hazard-free by simple techniques. We further analyze the timing constraints of pipelines based on the template, and then introduce two practical extensions of using the template. Compared with the prior work considering glitch-power reduction, pipelines using our proposed template can achieve significantly higher performance, lower power consumption, and less area overhead, with similar glitch-power reduction.
- H. Arif, M. A. Iqbal, M. Ali, and F. Bajwa, "Emerging aspects of asynchronous technology used for design of energy efficient computing platforms," IJCA, vol. 27, no. 9, pp. 7--12, 2011.Google Scholar
Cross Ref
- P. A. Beerel, R. O. Ozdaq, and M. Ferretti, A Designer's Guide to Asynchronous VLSI, CUP, 2010. Google ScholarDigital Library
- R. E. Bryant and D. R. O'Hallaron, Computer Systems: A Programmer's Perspective, Prentice Hall, 2011. Google ScholarDigital Library
- T. Chelcea, G. Venkataramani, and S. C. Goldstein, "Self-resetting latches for asynchronous micro-pipelines," in Proc. DAC, pp. 986--989, 2007. Google ScholarDigital Library
- G. Gopalakrishnan, P. Kudva, and E. Brunvand, "Peephole optimization of asynchronous macromodule networks," IEEE TVLSI, vol. 7, no. 1, pp. 30--37, 1999. Google ScholarDigital Library
- T. Hanyu and N. Onizawa, "Asynchronous protocol converter," U.S. Patent, 20130073771, 2013.Google Scholar
- M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design, Springer, 2008. Google ScholarDigital Library
- A. M. Lines, "Pipelined asynchronous circuits," Technical Report, Caltech, 1998. Google ScholarDigital Library
- S. M. Nowick and M. Singh, "High-performance asynchronous pipelines: An overview," IEEE Design & Test, vol. 28, no. 5, pp. 8--22, 2011. Google ScholarDigital Library
- N. C. Paver, The Design and Implementation of an Asynchronous Microprocessor, Ph.D. thesis, Manchester Univ., 1994.Google Scholar
- P. Schmid, "Intel's new weapon: Pentium 4 Prescott," Tom's Hardware, 2004.Google Scholar
- S. X. Shi, A. Ramalingam, D. Wang, and D. Z. Pan, "Latch modeling for statistical timing analysis," in Proc. DATE, pp. 1136--1141, 2008. Google ScholarDigital Library
- M. Singh and S. M. Nowick, "MOUSETRAP: High-speed transition-signaling asynchronous pipelines," IEEE TVLSI, vol. 15, no. 6, pp. 684--698, 2007. Google ScholarDigital Library
- M. Singh and S. M. Nowick, "The design of high-performance dynamic asynchronous pipelines: High-capacity style," IEEE TVLSI, vol. 15, no. 11, pp. 1270--1283, 2007. Google ScholarDigital Library
- J. Sparsø and S. Furber (Ed.), Principles of Asynchronous Circuit Design: A Systems Perspective, KAP, 2010. Google ScholarDigital Library
- I. Sutherland, "Micropipelines," ACM CACM, vol. 32, no. 6, pp. 720--738, 1989. Google ScholarDigital Library
- I. Sutherland and S. Fairbanks, "GasP: A minimal FIFO control," in Proc. ASYNC, pp. 46--53, 2001. Google ScholarDigital Library
- J. P. Uyemura, Introduction to VLSI Circuits and Systems, Wiley, 2002.Google Scholar
- V. I. Varshavsky (Ed.), Self-timed Control of Concurrent Processes: Models and Principles for Designing Aperiodic Logical Circuits in Computers and Discrete Systems, Springer, 1990.Google Scholar
- G. Venkataramani, T. Chelcea, and S. C. Goldstein, "Heterogeneous latch-based asynchronous pipelines," in Proc. ASYNC, pp. 83--92, 2008. Google ScholarDigital Library
- T. E. Williams, Self-Timed Rings and Their Application to Division, Ph.D. thesis, Stanford Univ., 1991. Google ScholarDigital Library
- C. G. Wong and A. J. Martin, "High-level synthesis of asynchronous systems by data-driven decomposition," in Proc. DAC, pp. 508--513, 2003. Google ScholarDigital Library
Index Terms
- A New Asynchronous Pipeline Template for Power and Performance Optimization
Recommendations
High-Performance Asynchronous Pipeline Circuits
ASYNC '96: Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and SystemsThis paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The first circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for data storage ...
Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm
This paper addresses the problem of identifying the minimum pipelining needed in an asynchronous circuit (e.g., number/size of pipeline stages/latches required) to satisfy a given performance constraint, thereby implicitly minimizing area and power for ...
Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template
This paper presents a new asynchronous design theory and a novel template for single-track handshaking that targets medium-to high-performance applications. Unlike other single-track templates, the proposed work supports multiple levels of logic per ...
Comments