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POLAR 2.0: An Effective Routability-Driven Placer

Published: 01 June 2014 Publication History

Abstract

A wirelength-driven placer without considering routability would lead to unroutable results. To mitigate routing congestion, there are two basic approaches: (1) minimizing the routing demand; (2) distributing the routing demand properly. In this paper, we propose a new placer POLAR 2.0 emphasizing both approaches. To minimize the routing demand, POLAR 2.0 attaches very high importance to maintaining a good wirelength-driven placement in the global placement stage. To distribute the routing demand, cells in congested regions are spread out by a novel routability-driven rough legalization in a global manner and by a history based cell inflation technique in a local manner. The experimental results based on ICCAD 2012 contest benchmark suite show that POLAR 2.0 outperforms all published academic routability-driven placers both in runtime and quality.

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  • (2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
  • (2023)PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247681(1-6)Online publication date: 9-Jul-2023
  • (2022)PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309301541:5(1495-1508)Online publication date: May-2022
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  1. POLAR 2.0: An Effective Routability-Driven Placer

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    cover image ACM Other conferences
    DAC '14: Proceedings of the 51st Annual Design Automation Conference
    June 2014
    1249 pages
    ISBN:9781450327305
    DOI:10.1145/2593069
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 June 2014

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    View all
    • (2023)Routability Optimization of Extreme Aspect Ratio Design through Non-uniform Placement Utilization and Selective Flip-flop StackingACM Transactions on Design Automation of Electronic Systems10.1145/357338728:4(1-19)Online publication date: 17-May-2023
    • (2023)PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247681(1-6)Online publication date: 9-Jul-2023
    • (2022)PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309301541:5(1495-1508)Online publication date: May-2022
    • (2021)AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643574(1-9)Online publication date: 1-Nov-2021
    • (2021)Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643544(1-8)Online publication date: 1-Nov-2021
    • (2021)Generalizable Cross-Graph Embedding for GNN-based Congestion Prediction2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD)10.1109/ICCAD51958.2021.9643446(1-9)Online publication date: 1-Nov-2021
    • (2021)Packing and Legalization Free Boolean Satisfiability-based Placement Algorithm for Heterogeneous FPGAsArabian Journal for Science and Engineering10.1007/s13369-021-06176-447:2(2255-2270)Online publication date: 21-Sep-2021
    • (2019)RePlAce: Advancing Solution Quality and Routability Validation in Global PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285922038:9(1717-1730)Online publication date: Sep-2019
    • (2019)FPGA Accelerated FPGA Placement2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00070(404-410)Online publication date: Sep-2019
    • (2019)Architecture‐aware routability‐driven placer for large‐scale mixed‐size designsIET Circuits, Devices & Systems10.1049/iet-cds.2018.551813:8(1209-1220)Online publication date: 12-Nov-2019
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