ABSTRACT
In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of an entire set of MOSFET model parameters using limited and incomplete IV measurements from on-chip monitor circuits. An important step in this method is the use of maximum-a-posteriori estimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction could also be used to characterize the statistical variations of MOSFETs with the significant benefit that some constraints required by the backward propagation of variance (BPV) method are relaxed.
- S. Yao, T.H. Morshed, D.D. Lu, S. Venugopalan, W. Xiong, C.R. Cleavelin, A.M. Niknejad, and C. Hu. Global parameter extraction for a multi-gate MOSFETs compact model. In IEEE International Conference on Microelectronic Test Structures (ICMTS), pages 194--197, 2010.Google ScholarCross Ref
- Q. Zhou, W. Yao, W. Wu, X. Li, Z. Zhu, and G. Gildenblat. Parameter extraction for the PSP MOSFET model by the combination of genetic and Levenberg-Marquardt algorithms. In IEEE International Conference on Microelectronic Test Structures (ICMTS), pages 137--142, 2009.Google ScholarCross Ref
- C.C. Mcandrew, Xin Li, I. Stevanovic, and G. Gildenblat. Extensions to backward propagation of variance for statistical modeling. IEEE Design Test of Computers, 27(2):36--43, 2010. Google ScholarDigital Library
- L. Yu, L. Wei, D. Antoniadis, I. Elfadel, and D. Boning. Statistical modeling with the virtual source mosfet model. In Design, Automation Test in Europe Conference Exhibition (DATE), 2013, pages 1454--1457, March 2013. Google ScholarDigital Library
- W. Zhang, X. Li, T. Liu, E. Acar, R.A. Rutenbar, and R.D. Blanton. Virtual probe: A statistical framework for low-cost silicon characterization of nanoscale integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(12): 1814--1827, 2011. Google ScholarDigital Library
- S. Reda and S.R. Nassif. Analyzing the impact of process variations on parametric measurements: Novel models and applications. In Design, Automation Test in Europe (DATE), pages 375--380, April 2009. Google ScholarDigital Library
- C. M. Bishop. Pattern Recognition and Machine Learning. Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2006. Google ScholarDigital Library
- S. Rakheja and D. Antoniadis. MVS 1.0.1 nanotransistor model (silicon), Nov 2013.Google Scholar
- A. Khakifirooz, O.M. Nayfeh, and D. Antoniadis. A simple semiempirical short-channel MOSFET current-voltage model continuous across all regions of operation and employing only physical parameters. IEEE Transactions on Electron Devices, 56(8): 1674--1680, Aug. 2009.Google ScholarCross Ref
- L. Wei, O. Mysore, and D. Antoniadis. Virtual-source-based self-consistent current and charge FET models: From ballistic to drift-diffusion velocity-saturation operation. IEEE Transactions on Electron Devices, (99):1--9, 2012.Google ScholarCross Ref
- L. Yu, O. Mysore, L. Wei, L. Daniel, D. Antoniadis, I. Elfadel, and D. Boning. An ultra-compact virtual source fet model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits. In Asia and South Pacific Design Automation Conference(ASPDAC), pages 521--526, 2013.Google Scholar
- L. Yu, S. Saxena, C. Hess, I. Elfadel, D. Antoniadis, and D. Boning. Efficient performance estimation with very small sample size via physical subspace projection and maximum a posteriori estimation. In Design, Automation and Test in Europe (DATE), 2014. Google ScholarDigital Library
- A. Khakifirooz and D.A. Antoniadis. Transistor performance scaling: The role of virtual source velocity and its mobility dependence. In International Electron Devices Meeting (IEDM), Dec. 2006.Google ScholarCross Ref
- H Liu, A. Singhee, R.A. Rutenbar, and L.R. Carley. Remembrance of circuits past: macromodeling by data mining in large analog design spaces. In Design Automation Conference (DAC), pages 437--442, 2002. Google ScholarDigital Library
- Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New Measurements
Recommendations
BSIM4 parameter extraction for tri-gate Si nanowire transistors
We investigated the BSIM4 parameter extraction procedure for tri-gate Si nanowire transistors with different geometries and fabrication processes. SPICE modeling tool was used to extract the parameter from Id-Vg to Id-Vd characteristics with liner and ...
Transistor Modeling for the VDSM Era
ISQED '00: Proceedings of the 1st International Symposium on Quality of Electronic DesignWe review field effect transistor modeling with emphasis on device parameter extraction for testing. We consider the physics-based universal charge control model, which allows us to describe the subthreshold, the weak inversion, and the strong inversion ...
Comments