skip to main content
10.1145/2593069.2593207acmotherconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

Row Based Dual-VDD Island Generation and Placement

Published: 01 June 2014 Publication History

Abstract

Power consumption has become a major consideration in nanometer chip design. Since the dynamic power is proportional to V dd2, and the static power is proportional to V dd, lowering power supply voltage is an efficient method to reduce the power usage.
In this paper, we adopt the row-based dual-supply voltage (DSV) scheme. DSV assigns a low power supply voltage to timing non-critical gates for the power saving. Contrary to the traditional region-based voltage island works, the row-based approach creates voltage islands along the circuit rows. This kind of fine grid voltage islands give more flexibility on gate voltage assignment such that the low voltage gates can be selected primarily based on timing and design logic, which in turn minimizes the shifter insertion. We present a two-stage flow to generate voltage islands for every two mirrored circuit rows and place gates legally inside each island. To the best of our knowledge, this is also the first work to cover latch and LCB (local clock buffer) handling and shifter placement in voltage island generation. The experimental results demonstrate the effectiveness and efficiency of our approach.

References

[1]
R.K. Ahuja, A.V. Goldberg, J.B. Orlin, R.E. Targan, Finding minimum-cost flows by double scaling, Mathematical programming, 1992.
[2]
R.K. Ahuja, T.L. Magnanti, and J.B. Orlin, Network Flows, Prentice Hall, 1993.
[3]
C.J. Alpert, Z. Li, G.-J. Nam, D.A. Papa, C.N. Sze, N. Viswanathan, Latch clustering with proximity to local clock buffers, Patent No. US20120110532 A1, 2012.
[4]
Y. Cai, B. Liu, Q. Zhou, and X. Hong, Voltage island generation in cell based dual-Vdd design. IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E90-A, 1, 267--273, 2007.
[5]
B.L.S. Ching, E.F. Young, K.C. K. Leung, and C. Chu, Post-placement voltage island generation. ICCAD, 2006.
[6]
T. Cormen, C. Leiserson, R. Rivest, and C. Stein, Introduction to Algorithms, the MIT press.
[7]
A. Correale, D.S. Kung, D.T. Lamb, Z. Pan, R. Puri and D. Wallach, Multiple voltage integrated circuit and design method therefore, Patent No. US7,111,266 B2, Sep, 2006.
[8]
H. Gabow, An efficient implementation of Edmond's algorithm for maximum weight matching on graphs, Journal of the ACM, Vol 23, Issue 2, pp.221--234, 1976.
[9]
L. Guo, Y. Cai, Q. Zhou, and X. Hong, Logic and layout aware voltage island generation for low power design. ASPDAC, 2007.
[10]
N. Karmarkar, A New Polynomial Time Algorithm for Linear Programming, Combinatorial, Vol 4, nr. 4, 1984.
[11]
W.-P. Lee, H.-Y. Liu, and Y.-W Chang, Voltage island aware floorplanning for power and timing optimization. ICCAD, 2006.
[12]
W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning. ICCAD, 2007.
[13]
M.K.Y. Leung, E. Chio, and E.F.Y. Young, Postplacement Voltage Island Generation, Trans. on Design Automation of Electronic Systems, Vol 17 Issue 1, Jan 2012.
[14]
B. Liu, Y. Cai, Q. Zhou, and X. Hong, Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs, ASPDAC, 2006.
[15]
Q. Ma, and E. F. Y. Young, Voltage island-driven floorplanning. ICCAD, 2007.
[16]
R.Ye, F. Yuan, Z. Sun, W.B. Jone and Q. Xu, Post-placement voltage island generation for timing-speculative circuits, DAC, 2013.
[17]
C. Yeh, Y. Kang, S. Shieh and J. Wang, Layout techniques supporting the use of dual supply voltages for cell-based designs, DAC, 1999.
[18]
S.I. Ward, N. Viswanathan, N.Y. Zhou, C.N. Sze, Z. Li, C.J. Alpert, and D.Z. Pan, Clock power minimization using structured latch templates and decision tree induction, ICCAD, 2013.
[19]
H. Wu, I.M. Liu, D.F. Wong and Y. Wang, Post-placement voltage island generation under performance requirement. ICCAD, 2005.
[20]
H. Wu, D.F. Wong, and L.-M Liu, Timing-constrained and voltage-island-aware voltage assignment. DAC, 2006.
[21]
H. Wu, D.F. Wong, I.-M Liu and Y. Wang, Placement-proximity-based voltage island grouping under performance requirement, Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol 26, No. 7, 2007.
[22]
H. Wu, D.F. Wong, Improving voltage assignment by outlier detection and incremental placement. DAC, 2007.

Cited By

View all
  • (2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
  • (2016)Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergenceIntegration, the VLSI Journal10.1016/j.vlsi.2015.09.00252:C(335-346)Online publication date: 1-Jan-2016

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences
DAC '14: Proceedings of the 51st Annual Design Automation Conference
June 2014
1249 pages
ISBN:9781450327305
DOI:10.1145/2593069
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

In-Cooperation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2014

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. clustering
  2. dual supply voltage
  3. placement

Qualifiers

  • Research-article
  • Research
  • Refereed limited

Conference

DAC '14

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)1
  • Downloads (Last 6 weeks)0
Reflects downloads up to 28 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
  • (2016)Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergenceIntegration, the VLSI Journal10.1016/j.vlsi.2015.09.00252:C(335-346)Online publication date: 1-Jan-2016

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media