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Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays

Published: 01 June 2014 Publication History

Abstract

Spin-Torque Transfer Random Access Memory (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the limited sense-margin poses challenge towards applicability of STTRAM. Reference voltage (Vref) biasing and clamp voltage (Vclamp) biasing are possible techniques to balance '0' and '1' sense margins for improved robustness. In this paper, we show that Vref and Vclamp biasing are more effective when employed on appropriately sized sense circuit. Our investigation also reveals that these two techniques can be used for meeting two different objectives namely, self-calibration and improved testability. We show that the proposed sizing and biasing technique can improve both robustness and testability while sacrificing minimum sense margin compared to conventional sense circuit that is designed to provide best sense margin.

References

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P. Zhou, et al. "Energy reduction for STT-RAM using early write termination." ICCAD, 2009.
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M. Rasquinha, et al. "An energy efficient cache design using spin torque transfer (stt) ram." ISLPED, 2010.
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Z. Sun, et al. "Multi retention level STT-RAM cache designs with a dynamic refresh scheme." Micro, 2011.
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J. Li, et al. "Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective." TVLSI, 2010
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Cited By

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  • (2022)Memory ChallengesSpringer Handbook of Semiconductor Devices10.1007/978-3-030-79827-7_17(603-633)Online publication date: 11-Nov-2022
  • (2016)Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.243728324:3(944-953)Online publication date: 1-Mar-2016
  • (2016)Overview of Circuits, Systems, and Applications of SpintronicsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.26013106:3(265-278)Online publication date: Sep-2016
  • Show More Cited By

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Published In

cover image ACM Other conferences
DAC '14: Proceedings of the 51st Annual Design Automation Conference
June 2014
1249 pages
ISBN:9781450327305
DOI:10.1145/2593069
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 01 June 2014

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Author Tags

  1. STTRAM
  2. design-for-test
  3. self-calibration
  4. sense margin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2022)Memory ChallengesSpringer Handbook of Semiconductor Devices10.1007/978-3-030-79827-7_17(603-633)Online publication date: 11-Nov-2022
  • (2016)Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall CachesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.243728324:3(944-953)Online publication date: 1-Mar-2016
  • (2016)Overview of Circuits, Systems, and Applications of SpintronicsIEEE Journal on Emerging and Selected Topics in Circuits and Systems10.1109/JETCAS.2016.26013106:3(265-278)Online publication date: Sep-2016
  • (2015)Impact of process-variations in STTRAM and adaptive boosting for robustnessProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757144(1431-1436)Online publication date: 9-Mar-2015
  • (2015)Domain Wall Memory-Layout, Circuit and Synergistic SystemsIEEE Transactions on Nanotechnology10.1109/TNANO.2015.239118514:2(282-291)Online publication date: Mar-2015

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