ABSTRACT
The increasing cost paid in clocking integrated circuits and combating timing variations forces designers to rethink asynchronous approaches to system realization. Among various techniques, quasi-delay-insensitive (QDI) design is promising due to its very relaxed timing assumption. Its expensive logic overhead, however, often nullifies its promise of performance and power improvements, and remains a major obstacle against its adoption. To overcome this obstacle, this paper proposes an efficient static performance analysis procedure and a synthesis flow for precharged half buffer (PCHB) and weak-conditioned half buffer (WCHB) circuit optimization. Experimental results demonstrate efficient performance analysis and effective area reduction under pipeline cycle time constraints.
- P. Beerel, A. Lines, M. Davies, and N.-H. Kim. Slack matching asynchronous designs. In Proc. Int'l Symp. on Asynchronous Circuits and Systems, pp. 184--194, 2006. Google ScholarDigital Library
- Berkeley Logic Synthesis and Verification Group. ABC: A system for sequential synthesis and verification. http://www.eecs.berkeley.edu/~alanmi/abc/Google Scholar
- P. Beerel, R. Ozdag, and M. Ferretti. A Designer's Guide to Asynchronous VLSI. Cambridge University Press, 2010. Google ScholarDigital Library
- K. Fant and S. Brandt. Null Convention Logic: A complete and consistent logic for asynchronous digital circuit synthesis. In Proc. Int'l Conf. on Application-Specific Systems, Architectures, and Processors, pp. 261--273, 1996. Google ScholarDigital Library
- J.-H. R. Jiang and S. Devadas. Logic synthesis in a nutshell. In Electronic Deisng Automation: Synthesis, Verification, and Test. L.-T. Wang, K.-T. Cheng, and Y.-W. Chang (Editors), Morgan Kaufmann Publishers, pp. 299--404, 2009.Google Scholar
- A. Kondratyev and K. Lwin. Design of asynchronous circuits using synchronous CAD tools. IEEE Design & Test of Computers, 19(4): 107--117, 2002. Google ScholarDigital Library
- A. Lines. Pipelined asynchronous circuits. M.S. thesis, California Institute of Technology, 1995.Google Scholar
- J. Magott. Performance evaluation of concurrent systems using Petri nets. Information Processing Letters, 18: 7--13, 1984.Google ScholarCross Ref
- A. Mishchenko, S. Chatterjee, and R. Brayton. DAG-aware AIG rewriting: A fresh look at combinational logic synthesis. In Proc. Design Automation Conference, pp. 532--535, 2006. Google ScholarDigital Library
- A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton. Combinational and sequential mapping with priority cuts. In Proc. Int'l Conf. on Computer-Aided Design, pp. 354--361, 2007. Google ScholarDigital Library
- A. Martin and M. Nyström. Asynchronous techniques for system-on-chip design. Proc. of the IEEE, 94(6): 1089--1120, 2006.Google ScholarCross Ref
- P. McGee and S. Nowick. An efficient algorithm for time separation of events in concurrent systems. In Proc. Int'l Conf. on Computer-Aided Design, pp. 180--187, 2007. Google ScholarDigital Library
- D. E. Muller. Asynrhconous logics and application to information processing. In Proc. Symp. Application of Switching Theory in Space Technology, pp. 289--297, 1963.Google Scholar
- Nanoscale Integration and Modeling Group. Predictive Technology Model. http://ptm.asu.edu/Google Scholar
- C. Ramamoorthy and G. S. Ho. Performance evaluation of asynchronous concurrent systems using Petri nets. IEEE Trans. Software Eng., SE-6(5): 440--449, 1980. Google ScholarDigital Library
- R. Reese, S. Smith, and M. Thornton. UNCLE --- An RTL approach to asynchronous design. In Proc. Int'l Symp. on Asynchronous Circuits and Systems, pp. 65--72, 2012. Google ScholarDigital Library
- J. Sparsø and S. Furber. Principles of Asynchronous Circuit Design. Kluwer Academic Publishers, 2001. Google ScholarDigital Library
- A. Smirnov and A. Taubin. Heuristic based throughput analysis and optimization of asynchronous pipelines. In Proc. Int'l Symp. on Asynchronous Circuits and Systems, pp. 162--172, 2009. Google ScholarDigital Library
Index Terms
- Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits
Recommendations
Scalable Synthesis of PCHB–WCHB Hybrid Quasi-Delay Insensitive Circuits
The increasing cost paid in clocking integrated circuits and combating timing variations forces designers to rethink asynchronous approaches to system realization. Among various techniques, quasi-delay insensitive design is promising due to its very ...
Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines
The class of quasi-delay-insensitive (QDI) asynchronous circuits provides a promising approach toward tolerating process variations. However, the fundamental assumption of QDI circuits is that some wires in such circuits are isochronic; this assumption ...
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits
ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation ConferenceThe Quasi-Delay-Insensitive (QDI) model assumes that all the forks are isochronic. The isochronic-fork assumption requires uniform wire delays and uniform switching thresholds of the gates associated with the forking branches. This paper presents a ...
Comments