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Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization

Published: 01 June 2014 Publication History

Abstract

Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. We introduce a heuristic framework---Walking Pads---to minimize transient voltage violations by optimizing power supply pad placement. We show that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. Our methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When we optimize pad placement using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. We also show that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

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Cited By

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  • (2024)Power Aware Placement of On-Chip Voltage RegulatorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331928543:2(654-666)Online publication date: Feb-2024
  • (2019)MTTF Enhancement Power-C4 Bump Placement OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.290404827:7(1633-1639)Online publication date: Jul-2019
  • (2019)From Layout to System: Early Stage Power Delivery and Architecture Co-ExplorationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443838:7(1291-1304)Online publication date: Jul-2019
  • Show More Cited By

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  1. Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization

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    cover image ACM Other conferences
    DAC '14: Proceedings of the 51st Annual Design Automation Conference
    June 2014
    1249 pages
    ISBN:9781450327305
    DOI:10.1145/2593069
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 01 June 2014

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    Author Tags

    1. Power distribution network
    2. Power pad allocation
    3. Voltage noise

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    View all
    • (2024)Power Aware Placement of On-Chip Voltage RegulatorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331928543:2(654-666)Online publication date: Feb-2024
    • (2019)MTTF Enhancement Power-C4 Bump Placement OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.290404827:7(1633-1639)Online publication date: Jul-2019
    • (2019)From Layout to System: Early Stage Power Delivery and Architecture Co-ExplorationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.283443838:7(1291-1304)Online publication date: Jul-2019
    • (2017)IGS: The Novel Fast IC Power Ground Network Optimization Flow Based on Improved Gauss-Seidel MethodAdvances in Science, Technology and Engineering Systems Journal10.25046/aj0203912:3(711-721)Online publication date: Jun-2017
    • (2017)ThermoGaterACM SIGARCH Computer Architecture News10.1145/3140659.308025045:2(120-132)Online publication date: 24-Jun-2017
    • (2017)ThermoGaterProceedings of the 44th Annual International Symposium on Computer Architecture10.1145/3079856.3080250(120-132)Online publication date: 24-Jun-2017
    • (2017)Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage RegulatorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.274294425:11(3019-3032)Online publication date: Nov-2017
    • (2016)A novel cross-layer framework for early-stage power delivery and architecture co-explorationProceedings of the 53rd Annual Design Automation Conference10.1145/2897937.2897969(1-6)Online publication date: 5-Jun-2016
    • (2016)Tolerating the Consequences of Multiple EM-Induced C4 Bump FailuresIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.250135324:6(2335-2344)Online publication date: Jun-2016
    • (2016)Parallel transient simulation of power delivery networks using model order reduction2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS)10.1109/EPEPS.2016.7835452(211-214)Online publication date: Oct-2016
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