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DWC: dynamic write consolidation for phase change memory systems

Published: 10 June 2014 Publication History

Abstract

Phase change memory (PCM) is promising to become an alternative main memory thanks to its better scalability and lower leakage than DRAM. However, the long write latency of PCM puts it at a severe disadvantage against DRAM. In this paper, we propose a Dynamic Write Consolidation (DWC) scheme to improve PCM memory system performance while reducing energy consumption. This paper is motivated by the observation that a large fraction of a cache line being written back to memory is not actually modified. DWC exploits the unnecessary burst writes of unmodified data to consolidate multiple writes targeting the same row into one write. By doing so, DWC enables multiple writes to be send within one. DWC incurs low implementation overhead and shows significant efficiency. The evaluation results show that DWC achieves up to 35.7% performance improvement, and 17.9% on average. The effective write latency are reduced by up to 27.7%, and 16.0% on average. Moreover, DWC reduces the energy consumption by up to 35.3%, and 13.9% on average.

References

[1]
Linked list traversal micro-benchmark. http://www.cs.illinois.edu/homes/zilles/llubenchmark.html.
[2]
Standard performance evaluation corporation. SPEC CPU 2006. http://www.spec.org/cpu2006/.
[3]
DDR3 SDRAM Standard JESD79--3F, 2010. http://www.jedec.org/standards-documents/docs/jesd-79--3d.
[4]
PIDS, ITRS, 2012. http://www.itrs.net/Links/2012ITRS/Home2012.htm.
[5]
J. H. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber. Future scaling of processor-memory interfaces. In SC, 2009.
[6]
J.-H. Ahn, J. Leverich, R. Schreiber, and N. Jouppi. Multicore DIMM: an energy efficient memory module with independently controlled DRAMs. Computer Architecture Letters, 2009.
[7]
F. Bedeschi, R. Fackenthal, C. Resta, E. M. Donze, M. Jagasivamani, E. C. Buda, F. Pellizzer, D. W. Chow, A. Cabrini, G. Calvi, et al. A bipolar-selected phase change memory featuring multi-level cell storage. IEEE Journal of Solid-State Circuits, 2009.
[8]
N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 2011.
[9]
T. Brewer. Instruction set innovations for the Convey HC-1 computer. IEEE Micro, 2010.
[10]
S. Cho and H. Lee. Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance. In MICRO, 2009.
[11]
A. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Mosse. Increasing pcm main memory lifetime. In DATE, 2010.
[12]
L. Jiang, B. Zhao, Y. Zhang, J. Yang, and B. Childers. Improving write operations in MLC phase change memory. In HPCA, 2012.
[13]
M. Joshi, W. Zhang, and T. Li. Mercury: A fast and energy-efficient multi-level cell based phase change memory system. In HPCA, 2011.
[14]
B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable DRAM alternative. In ISCA, 2009.
[15]
H. G. Lee, S. Baek, C. Nicopoulos, and J. Kim. An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems. In ICCD, 2011.
[16]
Y. Lee, S. Kim, S. Hong, and J. Lee. Skinflint DRAM system: Minimizing DRAM chip writes for low power. In HPCA, 2013.
[17]
C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. W. Keller. Energy management for commercial servers. Computer, 2003.
[18]
K. Lepak and M. Lipasti. Silent stores for free. In MICRO, 2000.
[19]
K. M. Lepak and M. H. Lipasti. On the value locality of store instructions. In ISCA, 2000.
[20]
S. Li, D. H. Yoon, K. Chen, J. Zhao, J. H. Ahn, J. B. Brockman, Y. Xie, and N. P. Jouppi. MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. In SC, 2012.
[21]
Z. Li, R. Zhou, and T. Li. Exploring high-performance and energy proportional interface for phase change memory systems. In HPCA, 2013.
[22]
K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, and S. Reinhardt. Understanding and designing new server architectures for emerging warehouse-computing environments. In ISCA, 2008.
[23]
N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi. CACTI 6.0: A tool to model large caches. Technical Report HPL-2009--85, HP Laboratories, 2009.
[24]
M. K. Qureshi, M. M. Franceschini, A. Jagmohan, and L. A. Lastras. PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. In ISCA, 2012.
[25]
M. K. Qureshi, M. M. Franceschini, L. A. Lastras-Monta\ no, and J. P. Karidis. Morphable memory system: a robust architecture for exploiting multi-level phase change memories. In ISCA, 2010.
[26]
M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano. Improving read performance of phase change memories via write cancellation and write pausing. In HPCA, 2010.
[27]
L. E. Ramos, E. Gorbatov, and R. Bianchini. Page placement in hybrid memory systems. In ICS, 2011.
[28]
J. Rice. Micron announces availability of phase change memory for mobile devices, 2012. http://investors.micron.com/releasedetail.cfm?ReleaseID=692563.
[29]
S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens. Memory access scheduling. In ISCA, 2000.
[30]
P. Rosenfeld, E. Cooper-Balis, and B. Jacob. DRAMSim2: A cycle accurate memory system simulator. Computer Architecture Letters, 2011.
[31]
S. Sardashti and D. A. Wood. Unifi: Leveraging non-volatile memories for a unified fault tolerance and idle power management technique. In ICS, 2012.
[32]
J. Shao and B. Davis. A burst scheduling access reordering mechanism. In HPCA, 2007.
[33]
A. N. Udipi, N. Muralimanohar, N. Chatterjee, R. Balasubramonian, A. Davis, and N. P. Jouppi. Rethinking DRAM design and organization for energy-constrained multi-cores. In ISCA, 2010.
[34]
D. H. Yoon, M. K. Jeong, and M. Erez. Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput. In ISCA, 2011.
[35]
J. Yue and Y. Zhu. Accelerating write by exploiting PCM asymmetries. In HPCA, 2013.
[36]
H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu. Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. In MICRO, 2008.
[37]
P. Zhou, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In ISCA, 2009.

Cited By

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  • (2023)OML-PCM: An Optical Multi-Level Phase Change Memory Architecture for Embedded Computing SystemsEngineering Research Express10.1088/2631-8695/ad0fc4Online publication date: 24-Nov-2023
  • (2022)Don't open rowProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530540(823-828)Online publication date: 10-Jul-2022
  • (2020)Exploiting inter- and intra-memory asymmetries for data mapping in hybrid tiered-memoriesProceedings of the 2020 ACM SIGPLAN International Symposium on Memory Management10.1145/3381898.3397215(100-114)Online publication date: 16-Jun-2020
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    cover image ACM Conferences
    ICS '14: Proceedings of the 28th ACM international conference on Supercomputing
    June 2014
    378 pages
    ISBN:9781450326421
    DOI:10.1145/2597652
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    Published: 10 June 2014

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    Author Tags

    1. performance optimization
    2. phase change memory
    3. write consolidation

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    Overall Acceptance Rate 629 of 2,180 submissions, 29%

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    Cited By

    View all
    • (2023)OML-PCM: An Optical Multi-Level Phase Change Memory Architecture for Embedded Computing SystemsEngineering Research Express10.1088/2631-8695/ad0fc4Online publication date: 24-Nov-2023
    • (2022)Don't open rowProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530540(823-828)Online publication date: 10-Jul-2022
    • (2020)Exploiting inter- and intra-memory asymmetries for data mapping in hybrid tiered-memoriesProceedings of the 2020 ACM SIGPLAN International Symposium on Memory Management10.1145/3381898.3397215(100-114)Online publication date: 16-Jun-2020
    • (2020)Improving phase change memory performance with data content aware accessProceedings of the 2020 ACM SIGPLAN International Symposium on Memory Management10.1145/3381898.3397210(30-47)Online publication date: 16-Jun-2020
    • (2020)MorLog: Morphable Hardware Logging for Atomic Persistence in Non-Volatile Main Memory2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA45697.2020.00057(610-623)Online publication date: May-2020
    • (2019)Enabling and Exploiting Partition-Level Parallelism (PALP) in Phase Change MemoriesACM Transactions on Embedded Computing Systems10.1145/335818018:5s(1-25)Online publication date: 7-Oct-2019
    • (2019)Writeback-Aware LLC Management for PCM-Based Main Memory SystemsACM Transactions on Design Automation of Electronic Systems10.1145/329200924:2(1-19)Online publication date: 10-Jan-2019
    • (2018)Energy, latency, and lifetime improvements in MLC NVM with enhanced WOM codeProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201737(554-559)Online publication date: 22-Jan-2018
    • (2018)WALL: A writeback-aware LLC management for PCM-based main memory systems2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342051(449-454)Online publication date: Mar-2018
    • (2018)Write Energy Reduction for PCM via Pumping Efficiency ImprovementACM Transactions on Storage10.1145/320013914:3(1-21)Online publication date: 26-Nov-2018
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