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Combinatorial spill code optimization and ultimate coalescing

Published: 12 June 2014 Publication History

Abstract

This paper presents a novel combinatorial model that integrates global register allocation based on ultimate coalescing, spill code optimization, register packing, and multiple register banks with instruction scheduling (including VLIW). The model exploits alternative temporaries that hold the same value as a new concept for ultimate coalescing and spill code optimization.
The paper presents Unison as a code generator based on the model and advanced solving techniques using constraint programming. Thorough experiments using MediaBench and a processor (Hexagon) that are typical for embedded systems demonstrate that Unison: is robust and scalable; generates faster code than LLVM (up to 41% with a mean improvement of 7%); possibly generates optimal code (for 29% of the experiments); effortlessly supports different optimization criteria (code size on par with LLVM).
Unison is significant as it addresses the same aspects as traditional code generation algorithms, yet is based on a simple integrated model and robustly can generate optimal code.

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Cited By

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  • (2020)Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW CompilersJournal of Signal Processing Systems10.1007/s11265-019-01493-2Online publication date: 17-Jan-2020
  • (2019)Combinatorial Register Allocation and Instruction SchedulingACM Transactions on Programming Languages and Systems10.1145/333237341:3(1-53)Online publication date: 2-Jul-2019
  • (2019)Survey on Combinatorial Register Allocation and Instruction SchedulingACM Computing Surveys10.1145/320092052:3(1-50)Online publication date: 18-Jun-2019
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cover image ACM Conferences
LCTES '14: Proceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
June 2014
174 pages
ISBN:9781450328777
DOI:10.1145/2597809
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 12 June 2014

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Author Tags

  1. combinatorial optimization
  2. instruction scheduling
  3. register allocation
  4. spill code optimization
  5. ultimate coalescing

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LCTES '14

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LCTES '14 Paper Acceptance Rate 16 of 51 submissions, 31%;
Overall Acceptance Rate 116 of 438 submissions, 26%

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Cited By

View all
  • (2020)Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW CompilersJournal of Signal Processing Systems10.1007/s11265-019-01493-2Online publication date: 17-Jan-2020
  • (2019)Combinatorial Register Allocation and Instruction SchedulingACM Transactions on Programming Languages and Systems10.1145/333237341:3(1-53)Online publication date: 2-Jul-2019
  • (2019)Survey on Combinatorial Register Allocation and Instruction SchedulingACM Computing Surveys10.1145/320092052:3(1-50)Online publication date: 18-Jun-2019
  • (2017)Complete and Practical Universal Instruction SelectionACM Transactions on Embedded Computing Systems10.1145/312652816:5s(1-18)Online publication date: 27-Sep-2017
  • (2016)Register allocation and instruction scheduling in UnisonProceedings of the 25th International Conference on Compiler Construction10.1145/2892208.2892237(263-264)Online publication date: 17-Mar-2016
  • (2016)Code generation for a SIMD architecture with custom memory organisation2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)10.1109/DASIP.2016.7853802(90-97)Online publication date: Oct-2016
  • (2015)Programming support for reconfigurable custom vector architecturesProceedings of the Sixth International Workshop on Programming Models and Applications for Multicores and Manycores10.1145/2712386.2712399(49-57)Online publication date: 7-Feb-2015
  • (2018)Compiling for VLIW DSPsHandbook of Signal Processing Systems10.1007/978-3-319-91734-4_27(979-1020)Online publication date: 14-Oct-2018
  • (2016)Register allocation and instruction scheduling in UnisonProceedings of the 25th International Conference on Compiler Construction10.1145/2892208.2892237(263-264)Online publication date: 17-Mar-2016
  • (2015)Modeling Universal Instruction SelectionPrinciples and Practice of Constraint Programming10.1007/978-3-319-23219-5_42(609-626)Online publication date: 13-Aug-2015

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