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GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction

Published: 29 December 2014 Publication History

Abstract

Timing Extraction identifies the delay of fine-grained components within an FPGA. From these computed delays, the delay of any path can be calculated. Moreover, a comparison of the fine-grained delays allows a detailed understanding of the amount and type of process variation that exists in the FPGA. To obtain these delays, Timing Extraction measures, using only resources already available in the FPGA, the delay of a small subset of the total paths in the FPGA. We apply Timing Extraction to the Logic Array Block (LAB) on an Altera Cyclone III FPGA to obtain a view of the delay down to near-individual LUT SRAM cell granularity, characterizing components with delays on the order of tens to a few hundred picoseconds with a resolution of ±3.2ps, matching the expected error bounds. This information reveals that the 65nm process used has, on average, random variation of σ μ =4.0% with components having an average maximum spread of 83ps. Timing Extraction also shows that as VDD decreases from 1.2V to 0.9V in a Cyclone IV 60nm FPGA, paths slow down, and variation increases from σ μ =4.3% to σ μ =5.8%, a clear indication that lowering VDD magnifies the impact of random variation.

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  • (2021)RWRoute: An Open-source Timing-driven Router for Commercial FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/349123615:1(1-27)Online publication date: 29-Nov-2021
  • (2021)Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC48570.2021.00011(17-24)Online publication date: Sep-2021
  • (2020)Safe Overclocking for CNN Accelerators Through Algorithm-Level Error DetectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.298105639:12(4777-4790)Online publication date: Dec-2020
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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems  Volume 7, Issue 4
January 2015
213 pages
ISSN:1936-7406
EISSN:1936-7414
DOI:10.1145/2699137
  • Editor:
  • Steve Wilton
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 29 December 2014
Accepted: 01 January 2014
Revised: 01 October 2013
Received: 01 May 2013
Published in TRETS Volume 7, Issue 4

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Author Tags

  1. Component-specific mapping
  2. in-system measurement
  3. variation characterization
  4. variation measurment

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Cited By

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  • (2021)RWRoute: An Open-source Timing-driven Router for Commercial FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/349123615:1(1-27)Online publication date: 29-Nov-2021
  • (2021)Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits2021 27th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC48570.2021.00011(17-24)Online publication date: Sep-2021
  • (2020)Safe Overclocking for CNN Accelerators Through Algorithm-Level Error DetectionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.298105639:12(4777-4790)Online publication date: Dec-2020
  • (2020)Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs2020 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT51103.2020.00023(103-111)Online publication date: Dec-2020
  • (2019)Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAsProceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies10.1145/3337801.3337818(1-6)Online publication date: 6-Jun-2019
  • (2019)Characterization of Long Wire Data Leakage in Deep Submicron FPGAsProceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3289602.3293923(292-297)Online publication date: 20-Feb-2019
  • (2019)An Open-Source Lightweight Timing Model for RapidWright2019 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT47387.2019.00028(171-178)Online publication date: Dec-2019
  • (2019)Timing-Aware Routing in the RapidWright Framework2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00014(24-30)Online publication date: Sep-2019
  • (2019)Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage2019 29th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2019.00011(1-8)Online publication date: Sep-2019
  • (2018)Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP)ACM Transactions on Reconfigurable Technology and Systems10.1145/315822911:1(1-23)Online publication date: 26-Jan-2018
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