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A parallelizing compiler for multicore systems

Published: 10 June 2014 Publication History

Abstract

This manuscript summarizes the main ideas introduced in [1]. We propose a compiler that automatically transforms a sequential application into a parallel counterpart for multicore processors. It is based on an intermediate representation, named KIR, which exposes multiple levels of parallelism and hides the complexity of the implementation details thanks to the domain-independent kernels (e.g., assignment, reduction). The effectiveness and performance of our approach, built on top of GCC, has been tested with a large variety of codes.

References

[1]
J. M. Andión et al. A Novel Compiler Support for Automatic Parallelization on Multicore Systems. Parallel Comput., 39(9), 2013.
[2]
M. Arenaz et al. XARK: An Extensible Framework for Automatic Recognition of Computational Kernels. ACM Trans. Program. Lang. Syst., 30(6), 2008.
[3]
M.-W. Benabderrahmane et al. The Polyhedral Model is more Widely Applicable than You Think. In CC, 2010.
[4]
U. Bondhugula et al. A Practical Automatic Polyhedral Parallelizer and Locality Optimizer. In PLDI, 2008.
[5]
A. Canedo et al. Automatic Parallelization of Simulink Applications. In CGO, 2010.
[6]
B. Franke and M. O'Boyle. Array Recovery and High-Level Transformations for DSP Applications. ACM Trans. Embed. Comput. Syst., 2(2), 2003.
[7]
S. Girbal et al. Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies. Int. J. Parallel Program., 34(3), 2006.
[8]
E. Gutiérrez et al. Data Partitioning-Based Parallel Irregular Reductions. Concurr. Comput.: Pract. Exper., 16(2--3), 2004.
[9]
J. Huang et al. Decoupled Software Pipelining Creates Parallelization Opportunities. In CGO, 2010.
[10]
D. Liu et al. Optimally Maximizing Iteration-Level Loop Parallelism. IEEE Trans. Parallel Distrib. Syst., 23(3), 2012.
[11]
G. Ottoni et al. Automatic Thread Extraction with Decoupled Software Pipelining. In MICRO, 2005.
[12]
S. Sato and H. Iwasaki. Automatic Parallelization via Matrix Multiplication. In PLDI, 2011.
[13]
H. Vandierendonck et al. The Paralax Infrastructure: Automatic Parallelization with a Helping Hand. In PACT, 2010.

Cited By

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  • (2017)A Case Study of Performance Optimization in a Heterogeneous Environment2017 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)10.1109/SBAC-PADW.2017.11(13-18)Online publication date: Oct-2017

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  1. A parallelizing compiler for multicore systems

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    cover image ACM Other conferences
    SCOPES '14: Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems
    June 2014
    162 pages
    ISBN:9781450329415
    DOI:10.1145/2609248
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    • EDAA: European Design Automation Association

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    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 10 June 2014

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    Author Tags

    1. automatic parallelization
    2. compiler intermediate representation
    3. domain-independent kernel
    4. multicore processor

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    • Research-article

    Funding Sources

    • FEDER Funds of the European Union and the Ministry of Economy and Competitiveness of Spain
    • FPU Program of the Ministry of Education of Spain
    • Galician Government

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    SCOPES '14
    Sponsor:
    • EDAA

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    Overall Acceptance Rate 38 of 79 submissions, 48%

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    Cited By

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    • (2017)A Case Study of Performance Optimization in a Heterogeneous Environment2017 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW)10.1109/SBAC-PADW.2017.11(13-18)Online publication date: Oct-2017

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