Jason Luu
Jonathan Rose
Abstract
Exploring architectures for large, modern FPGAs requires sophisticated software that can model and target hypothetical devices. Furthermore, research into new CAD algorithms often requires a complete and open source baseline CAD flow. This article describes recent advances in the open source Verilog-to-Routing (VTR) CAD flow that enable further research in these areas. VTR now supports designs with multiple clocks in both timing analysis and optimization. Hard adder/carry logic can be included in an architecture in various ways and significantly improves the performance of arithmetic circuits. The flow now models energy consumption, an increasingly important concern. The speed and quality of the packing algorithms have been significantly improved. VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. We also release new FPGA architecture files and models that are much closer to modern commercial architectures, enabling more realistic experiments. Finally, we show that while this version of VTR supports new and complex features, it has a 1.5× compile time speed-up for simple architectures and a 6× speed-up for complex architectures compared to the previous release, with no degradation to timing or wire-length quality.
- C. Ababei, H. Mogal, and K. Barzargan. 2006. Three-dimensional place and route for FPGAs. IEEE Trans. CAD. 1132--1140. Google Scholar
Digital Library
- M. Abdelfattah and V. Betz. 2013. The power of communication: energy-efficient NoCs for FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications. 1--8.Google Scholar
- Altera. 2009. Stratix IV Device Family Overview. http://www.altera.com/literature/hb/stratix-iv/stx4_siv51001.pdf.Google Scholar
- Altera. 2012a. PowerPlay Early Power Estimator: User Guide. http://www.altera.com/support/devices/estimator/pow-powerplay.jsp.Google Scholar
- Altera. 2012b. Stratix V Device family overview. http://www.altera.com/devices/fpga/stratix-fpgas/stratix-v/stxv-index.jsp.Google Scholar
- Altera. 2013. Quartus II Version 13.0 Handbook. http://www.altera.com/.Google Scholar
- V. Betz and J. Rose. 2000. Automatic generation of FPGA routing architectures from high-level descriptions. In Proceedings of the ACM International Symposium on FPGAs. 175--184. Google ScholarDigital Library
- V. Betz, J. Rose, and A. Marquardt. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Norwell, MA. Google ScholarDigital Library
- Y. Cao. 2008. Berkeley predictive technology model. http://ptm.asu.edu/.Google Scholar
- C. Chiasson and V. Betz. 2013. COFFE: Fully-automated transistor sizing for FPGAs. In Proceedings of the IEEE International Conference on Field-Programmable Technology.Google Scholar
- K. Chung and J. Rose. 1992. TEMPT: Technology mapping for the exploration of FPGA architectures with hard-wired connections. In Proceedings of the ACM/IEEE Design Automation Conference. 361--367. Google ScholarDigital Library
- S. Gangadharan and S. Churiwala. 2013. Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints. Springer. Google ScholarDigital Library
- J. Goeders and S. Wilton. 2012. VersaPower: Power estimation for diverse FPGA architectures. In Proceedings of the IEEE International Conference on Field Programmable Technology. 229--234.Google Scholar
- H.-C. Hsieh, W. Carter, J. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin, L. Tinkey, and R. Kanazawa. 1990. Third-generation architecture boosts speed and density of field-programmable gate arrays. In Proceedings of the IEEE Custom Integrated Circuits Conference. 31.2/1--31.2/7.Google Scholar
- M. Hutton, D. Karchmer, B. Archell, and J. Govig. 2005. Efficient static timing analysis and applications using edge masks. In Proceedings of the ACM International Symposium on FPGAs. 175--183. Google ScholarDigital Library
- ITRS. 2011. Interconnect chapter. http://www.itrs.net/Links/2011ITRS/2011Chapters/2011Interconnect.pdf.Google Scholar
- P. Jamieson, K. Kent, F. Gharibian, and L. Shannon. 2010. Odin II: An open-source Verilog HDL synthesis tool for CAD research. In Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines. 149--156. Google ScholarDigital Library
- P. Jamieson, W. Luk, S. J. Wilton, and G. A. Constantinides. 2009. An energy and power consumption analysis of FPGA routing architectures. In Proceedings of the IEEE International Conference on Field Programmable Technology. 324--327.Google Scholar
- I. Kuon and J. Rose. 2008. Automated transistor sizing for fpga architecture exploration. In Proceedings of the 45th Annual Design Automation Conference (DAC'08). ACM, New York, 792--795. Google ScholarDigital Library
- J. Lamoureux and S. J. Wilton. 2006. Activity estimation for field-programmable gate arrays. In Proceedings of the International Conference on Field Programmable Logic and Applications. 1--8.Google Scholar
- LATTICE. 2012. ECP3 family. http://www.latticesemi.com/products/fpga/ecp3/index.cfm.Google Scholar
- C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings. 2011. Rapid-Smith: Do-It-yourself CAD tools for Xilinx FPGAs. In Proceedings of the International Conference on Field-Programable Logic and Applications. 349--355. Google ScholarDigital Library
- F. Li and L. He. 2005. Power Modeling and Characteristics of Field Programmable Gate Arrays. IEEE Trans. CAD 24, 11, 1712--1724. Google ScholarDigital Library
- J. Libby, A. Furrow, P. O'Brien, and K. Kent. 2011. A framework for verifying functional correctness in Odin II. In Proceedings of the IEEE International Conference on Field-Programmable Technology. 1--6.Google Scholar
- J. Luu, J. Anderson, and J. Rose. 2011. Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. In Proceedings of the ACM International Symposium on FPGAs. 227--236. Google ScholarDigital Library
- J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. M. Fang, and J. Rose. 2009. VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. In Proceedings of the ACM International Symposium on FPGAs. 133--142. Google ScholarDigital Library
- Microsemi. 2013. Smartfusion2 SoC FPGAs. http://www.microsemi.com/fpga-soc/soc-fpga/smartfusion2.Google Scholar
- A. Mishchenko. 2009. ABC: A system for sequential synthesis and verification. http://www.eecs.berkeley. edu/alanmi/abc.Google Scholar
- K. Murray, S. Whitty, J. Luu, S. Liu, and V. Betz. 2013. Titan: Enabling large and realistic benchmarks for FPGAs. In Proceedings of the IEEE International Conference on Field-Programmable Logic and Applications. 1--8.Google Scholar
- K. Nasartschuk, R. Herpers, and K. Kent. 2012. Visualization support for FPGA architecture exploration. In Proceedings of the IEEE International Symposiumon Rapid System Prototyping. 128--134.Google Scholar
- K. K. W. Poon, S. J. E. Wilton, and A. Yan. 2005. A detailed power model for field-programmable gate arrays. ACM Trans. Des. Autom. Electron. Syst. 10, 2, 279--302. Google ScholarDigital Library
- J. Rose, J. Luu, C. W. Yu, O. Densmore, J. Goeders, A. Somerville, K. B. Kent, P. Jamieson, and J. Anderson. 2012. The VTR project: Architecture and CAD for FPGAs from Verilog to routing. In Proceedings of the ACM International Symposium on FPGAs. 77--86. Google ScholarDigital Library
- A. Sharma, C. Ebeling, and S. Hauck. 2005. Architecture-adaptive routability-driven placement for FPGAs. In Proceedings of the International Conference on Field-Programmable Logic and Applications. 427--432. Google ScholarDigital Library
- W. W.-K. Shum and J. H. Anderson. 2011. FPGA glitch power analysis and reduction. In Proceedings of the IEEE/ACM International Symposium on Low-Power Electronics and Design. 27--32. Google ScholarDigital Library
- A. Somerville and K. Kent. 2012. Improving memory support in the VTR flow. In Proceedings of the International Conference on Field Programmable Logic and Applications. 197--202.Google Scholar
- N. Steiner, A. Wood, H. Shojaei, J. Couch, P. Athanas, and M. French. 2011. Torc: Towards an open-source tool flow. In Proceedings of the ACM International Symposium on FPGAs. 41--44. Google ScholarDigital Library
- N. Weste and D. Harris. 2010. CMOS VLSI Design: A Circuits and Systems Perspective 4th Ed. Addison Wesley. Google ScholarDigital Library
- H. Wong, V. Betz, and J. Rose. 2011. Comparing FPGA vs. custom CMOS and the impact on processor microarchitecture. In Proceedings of the ACM International Symposium on FPGAs. 5--14. Google ScholarDigital Library
- N.-S. Woo. 1995. Revisiting the cascade circuit in logic cells of lookup table based FPGAs. In Proceedings of the ACM International Symposium on FPGAs. 90--96. Google ScholarDigital Library
- Xilinx. 2011. Xilinx Power Estimator User Guide.Google Scholar
- Xilinx. 2013a. Vivado design software. http://www.xilinx.com/.Google Scholar
- Xilinx. 2013b. Xilinx Virtex-7 family overview. http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/index.htm.Google Scholar
Index Terms
- VTR 7.0: Next Generation Architecture and CAD System for FPGAs
Recommendations
The VTR project: architecture and CAD for FPGAs from verilog to routing
FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate ArraysTo facilitate the development of future FPGA architectures and CAD tools -- both embedded programmable fabrics and pure-play FPGAs -- there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described ...
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only)
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arraysAn Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at different times. Application circuits are initially placed and routed on an FPGA in such a way that ...
Application-Specific FPGA using heterogeneous logic blocks
This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) ...
Comments