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Empirically derived abstractions in uncore power modeling for a server-class processor chip

Published: 11 August 2014 Publication History

Abstract

Early-stage power modeling is an essential aspect of the process of defining efficient, yet high-performance microarchitectures. Pre-silicon power modeling has been an active area of research and development for well over a decade, although primarily focused on the processor cores. In this paper, we examine the challenge of developing practical abstractions in uncore power modeling in an industrial setting. We report a systematic methodology of abstractions in modeling with a focus on key uncore elements of the POWER8TM processor chip from IBM. The results show that the active power of these uncore elements can be modeled with acceptable levels of precision, by: (a) using just a few activity markers: e.g. reads, writes, retries and snoops; and (b) using a small set of systematically crafted microbenchmark stress test cases to measure the activity frequencies on a detailed, cycle- and latch-accurate RTL reference model.

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Cited By

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  • (2022)AI accelerator on IBM Telum processorProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3533042(1012-1028)Online publication date: 18-Jun-2022
  • (2021)Energy efficiency boost in the AI-infused POWER10 processorProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00012(29-42)Online publication date: 14-Jun-2021
  • (2019)Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2019.00099(470-475)Online publication date: Jan-2019
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cover image ACM Conferences
ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design
August 2014
398 pages
ISBN:9781450329750
DOI:10.1145/2627369
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 August 2014

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Author Tags

  1. energy-efficient design
  2. levels of abstraction
  3. power modeling
  4. power proxy
  5. speed-accuracy trade-offs

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ISLPED '14 Paper Acceptance Rate 63 of 184 submissions, 34%;
Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all
  • (2022)AI accelerator on IBM Telum processorProceedings of the 49th Annual International Symposium on Computer Architecture10.1145/3470496.3533042(1012-1028)Online publication date: 18-Jun-2022
  • (2021)Energy efficiency boost in the AI-infused POWER10 processorProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00012(29-42)Online publication date: 14-Jun-2021
  • (2019)Heterogeneity Aware Power Abstraction for Hierarchical Power Analysis2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2019.00099(470-475)Online publication date: Jan-2019
  • (2019)Heterogeneity aware power abstractions for dynamic power dominated FinFET‐based microprocessorsIET Computers & Digital Techniques10.1049/iet-cdt.2019.003113:6(524-531)Online publication date: 4-Sep-2019
  • (2016)FVCAGProceedings of the 2016 International Symposium on Low Power Electronics and Design10.1145/2934583.2934633(260-265)Online publication date: 8-Aug-2016

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