research-article

Design and CAD methodologies for low power gate-level monolithic 3D ICs

Authors:

Shreepad A. Panth,

Kambiz Samadi,

Yang Du,

Sung Kyu LimAuthors Info & Claims

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

Pages 171 - 176

https://doi.org/10.1145/2627369.2627642

Published: 11 August 2014 Publication History

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Abstract

In a gate-level monolithic 3D IC (M3D), all the transistors in a single logic gate occupy the same tier, and gates in different tiers are connected using nano-scale monolithic inter-tier vias. This design style has the benefit of the superior power-performance quality offered by flat implementations (unlike block-level M3D), and zero total silicon area overhead compared to 2D (unlike transistor-level M3D). In this paper we develop, for the first time, a complete RTL-to-GDSII design flow for gate-level M3D. Our tool flow is based on commercial tools built for 2D ICs and enhanced with our 3D specific methodologies. We use this flow along with a 28nm PDK to build layouts for the OpenSPARC T2 core. Our simulations show that at the same performance, gate-level M3D offers 16% total power reduction with 0% area overhead compared to commercial quality 2D IC designs.

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Jeong EKim TPark HNakamura YWang Y(2025)PPA-Aware Tier Partitioning for 3D IC Placement with ILP FormulationProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697733(879-885)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697733
Hung SBhoumik PChaudhuri ABanerjee SChakrabarty K(2024)Design-for-Test Solutions for 3-D Integrated CircuitsIntegrated Circuits and Systems10.23919/ICS.2024.34196291:1(3-17)Online publication date: Mar-2024
https://doi.org/10.23919/ICS.2024.3419629
Kim SPark H(2024)Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.335760043:7(1944-1956)Online publication date: Jul-2024
https://doi.org/10.1109/TCAD.2024.3357600
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Index Terms

Design and CAD methodologies for low power gate-level monolithic 3D ICs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

August 2014

398 pages

ISBN:9781450329750

DOI:10.1145/2627369

General Chairs:
Yuan Xie
UCSB, USA
,
Tanay Karnik
Intel, USA
,
Program Chairs:
Muhammad M. Khellah
Intel, USA
,
Renu Mehra
Synopsys, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 11 August 2014

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ISLPED'14: International Symposium on Low Power Electronics and Design

August 11 - 13, 2014

California, La Jolla, USA

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ISLPED '14 Paper Acceptance Rate 63 of 184 submissions, 34%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Jeong EKim TPark HNakamura YWang Y(2025)PPA-Aware Tier Partitioning for 3D IC Placement with ILP FormulationProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697733(879-885)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697733
Hung SBhoumik PChaudhuri ABanerjee SChakrabarty K(2024)Design-for-Test Solutions for 3-D Integrated CircuitsIntegrated Circuits and Systems10.23919/ICS.2024.34196291:1(3-17)Online publication date: Mar-2024
https://doi.org/10.23919/ICS.2024.3419629
Kim SPark H(2024)Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.335760043:7(1944-1956)Online publication date: Jul-2024
https://doi.org/10.1109/TCAD.2024.3357600
Liao PZhao YGuo DLin YYu B(2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
https://doi.org/10.1109/TCAD.2023.3347293
Mansoor AChrzanowska-Jeske M(2024)SERS-3DPlace: Ensemble Reinforcement Learning for 3D Monolithic Placement2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10558181(1-5)Online publication date: 19-May-2024
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Park SPark H(2024)Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration2024 International Conference on Electronics, Information, and Communication (ICEIC)10.1109/ICEIC61013.2024.10457092(1-4)Online publication date: 28-Jan-2024
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Chang KLim S(2024)Design and Tool Solutions for Monolithic Three-Dimensional Integrated CircuitsHandbook of Computer Architecture10.1007/978-981-97-9314-3_65(751-804)Online publication date: 21-Dec-2024
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Chang KLim S(2024)Design and Tool Solutions for Monolithic Three-Dimensional Integrated CircuitsHandbook of Computer Architecture10.1007/978-981-15-6401-7_65-1(1-54)Online publication date: 27-Mar-2024
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Mansoor AChrzanowska-Jeske MJeske M(2024)AI-Enabled Placement for 2D and 3D ICsAI-Enabled Electronic Circuit and System Design10.1007/978-3-031-71436-8_6(189-223)Online publication date: 17-Oct-2024
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Dewan MLin SKim D(2023)Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC RoutingACM Transactions on Design Automation of Electronic Systems10.1145/362695829:1(1-28)Online publication date: 18-Dec-2023
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Recommendations

Power benefit study for ultra-high density transistor-level monolithic 3D ICs

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs

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