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Synergistic circuit and system design for energy-efficient and robust domain wall caches

Published: 11 August 2014 Publication History

Abstract

Non-volatile memories are gaining significant attention for embedded cache application due to their low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits per cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and retention. However, it suffers from poor write latency, shift latency, shift power and write power. DWM is sequential in nature and latency of read/write operations depends on the offset of the bit from the read/write head. This paper investigates the circuit design challenges such as bitcell layout, head positioning, utilization factor of the nanowire, shift power, shift latency and provides solutions to deal with these issues. A synergistic system is proposed by combining circuit techniques such as merged read/write heads (for compact layout), flipped-bitcell and shift gating (for shift power optimization), wordline (WL) strapping (for access latency), shift circuit design with micro-architectural techniques such as segmented cache to realize energy-efficient and robust DWM cache. Simulations show 3-33% better performance and 1.25X-14.4X better power over a wide range of PARSEC benchmarks.

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  • (2023) ROLLED: R acetrack Memory O ptimized L inear L ayout and E fficient D ecomposition of Decision Trees IEEE Transactions on Computers10.1109/TC.2022.319709472:5(1488-1502)Online publication date: 1-May-2023
  • (2022)BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316119841:12(5288-5298)Online publication date: Dec-2022
  • (2020)RNNFastACM Journal on Emerging Technologies in Computing Systems10.1145/339967016:4(1-27)Online publication date: 18-Sep-2020
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  1. Synergistic circuit and system design for energy-efficient and robust domain wall caches

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        cover image ACM Conferences
        ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design
        August 2014
        398 pages
        ISBN:9781450329750
        DOI:10.1145/2627369
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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        Published: 11 August 2014

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        Author Tags

        1. cache segregation
        2. design domain wall memory
        3. shift power
        4. synergistic systems

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        ISLPED '14 Paper Acceptance Rate 63 of 184 submissions, 34%;
        Overall Acceptance Rate 398 of 1,159 submissions, 34%

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        View all
        • (2023) ROLLED: R acetrack Memory O ptimized L inear L ayout and E fficient D ecomposition of Decision Trees IEEE Transactions on Computers10.1109/TC.2022.319709472:5(1488-1502)Online publication date: 1-May-2023
        • (2022)BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316119841:12(5288-5298)Online publication date: Dec-2022
        • (2020)RNNFastACM Journal on Emerging Technologies in Computing Systems10.1145/339967016:4(1-27)Online publication date: 18-Sep-2020
        • (2018)Design and Data Management for Magnetic Racetrack Memory2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351681(1-4)Online publication date: May-2018
        • (2018)A Novel Reflection Removal Algorithm Using the Light Field Camera2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351103(1-5)Online publication date: 2018
        • (2018)K-SVD Based Denoising Algorithm for DoFP Polarization Image Sensors2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8350922(1-5)Online publication date: May-2018
        • (2017)Leveraging access port positions to accelerate page table walk in DWM-based main memoryProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130720(1454-1459)Online publication date: 27-Mar-2017
        • (2017)Leveraging access port positions to accelerate page table walk in DWM-based main memoryDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927220(1450-1455)Online publication date: Mar-2017
        • (2017)Coding for Efficient Caching in Multicore Embedded Systems2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2017.59(296-301)Online publication date: Jul-2017
        • (2016)A Technique for Improving Lifetime of Non-Volatile Caches Using Write-MinimizationJournal of Low Power Electronics and Applications10.3390/jlpea60100016:1(1)Online publication date: 18-Jan-2016
        • Show More Cited By

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