research-article

StoRM: a stochastic recognition and mining processor

Authors:

Vinay K. Chippa,

Swagath Venkataramani,

Anand RaghunathanAuthors Info & Claims

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

Pages 39 - 44

https://doi.org/10.1145/2627369.2627645

Published: 11 August 2014 Publication History

Abstract

Recognition and Mining are emerging application domains that are becoming prevalent across the entire spectrum of computing platforms, and place very high demands on their capabilities. We propose a Stochastic Recognition and Mining processor (StoRM), which uses Stochastic Computing (SC) to efficiently realize computational kernels from these domains. Stochastic computing facilitates compact, power-efficient realization of arithmetic operations by representing and processing information as pseudo-random bit-streams. However, the overhead of conversion between representations, and the exponential relationship between precision and bit-stream length, are key challenges that limit the efficiency of stochastic designs. The proposed architecture for StoRM consists of a 2D array of Stochastic Processing Elements (StoPEs) with a streaming memory hierarchy, enabling binary-to-stochastic conversion to be amortized across rows or columns of StoPEs. We propos vector processing and segmented stochastic processing in the StoPEs to mitigate the unfavorable tradeoff between precision and bit-stream length. We also exploit the compactness of StoPEs to increase parallelism, thereby improving performance and energy efficiency. Finally, leveraging the resilience of RM applications to approximations in their computations, we design StoRM to support modulation of the stochastic bit-stream length, and utilize this capability to to optimize energy for a desired output quality. StoRM achieves 2-3X energy-delay improvements over a conventional design without sacrificing output quality, and upto 10X (20X) improvements when upto 5% (10%) loss in output quality is allowed. Our results also demonstrate that the proposed design techniques greatly enhance the applicability and benefits of stochastic computing.

References

[1]

C. Chu et. al. Map-reduce for machine learning on multicore. Proc. NIPS, 2007.

[2]

J. Meng et. al. Best-effort parallel execution framework for recognition and mining applications. Proc. IPDPS, 2009.

Digital Library

[3]

A. Majumdar et. al. A massively parallel, energy efficient programmable accelerator for learning and classification. ACM Trans. Architecture Code Optimization, 2012.

Digital Library

[4]

R. Iyer et. al. CogniServe: Heterogeneous server architecture for large-scale recognition. IEEE MICRO, 2011.

Digital Library

[5]

S. Lee et. al. A 345mw heterogeneous many-core processor with an intelligent inference engine for robust object recognition. In Proc. ISSCC, 2010.

[6]

B. R. Gaines. Stochastic computing. In Proc. SJCC, 1967.

Digital Library

[7]

A. Alaghi et. al. Survey of stochastic computing. Trans. Embedded Computing Systems, 2013.

Digital Library

[8]

V. K. Chippa et. al. Analysis and characterization of inherent application resilience for approximate computing. In Proc. DAC, 2013.

Digital Library

[9]

V. C. Gaudet. Iterative decoding using stochastic computation. Electronics Letters, 2003.

[10]

P. Li et. al. Using stochastic computing to implement digital image processing algorithms. In Proc. ICCD, 2011.

Digital Library

[11]

W. Qian et. al. An architecture for fault-tolerant computation with stochastic logic. IEEE Trans. on Computers, 2011.

Digital Library

[12]

A. Alaghi et. al. Stochastic circuits for real-time image-processing applications. In Proc. DAC, 2013.

Digital Library

[13]

S. T. Chakradhar et. al. Best-effort computing: Re-thinking parallel software and hardware. In Proc. DAC, 2010.

Digital Library

[14]

V. K. Chippa, H. Jayakumar, D. Mohapatra, K. Roy, and A. Raghunathan. Energy-efficient recognition and mining processor using scalable effort design. In Proc. CICC, 2013.

[15]

R. Hegde et. al. Energy-efficient signal Processing via algorithmic noise-tolerance. In Proc. ISLPED, 1999.

Digital Library

[16]

K. Palem et. al. Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects. In Proc. CASES, 2009.

Digital Library

[17]

V. Gupta et. al. IMPACT: Imprecise adders for low-power approximate computing. In Proc. ISLPED, 2011.

Digital Library

[18]

A. Lingamneni et al. Energy parsimonious circuit design through probabilistic pruning. In Proc. DATE, 2011.

[19]

S. Venkataramani et. al. SALSA: Systematic logic synthesis of approximate circuits. In Proc. DAC, 2012.

Digital Library

[20]

V. K. Chippa et. al. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency. In Proc. DAC, 2010.

Digital Library

[21]

S. Venkataramani et. al. Quality programmable vector processors for approximate computing. In Proc. MICRO, 2013.

Digital Library

[22]

W. J. Poppelbaum et. al. Stochastic computing elements and systems. In Proc. JCC, 1967.

Digital Library

[23]

B. D. Brown et. al. Stochastic neural computation. I. Computational elements. IEEE Trans. on Computers, 2001.

Digital Library

[24]

J. M. Quero et. al. Continuous time controllers using digital programmable devices. In Proc. IECON, 1999.

Cited By

Li TRomaszkan WPamarti SGupta P(2023)REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328428942:12(4423-4435)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3284289
Chen ZMa YWang Z(2022)Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.316652469:7(2707-2720)Online publication date: Jul-2022
https://doi.org/10.1109/TCSI.2022.3166524
Romaszkan WLi TGupta P(2022)SASCHA—Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319750341:11(4169-4180)Online publication date: Nov-2022
https://doi.org/10.1109/TCAD.2022.3197503
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Index Terms

StoRM: a stochastic recognition and mining processor
1. Hardware
  1. Very large scale integration design

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cover image ACM Conferences

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

August 2014

398 pages

ISBN:9781450329750

DOI:10.1145/2627369

General Chairs:
Yuan Xie
UCSB, USA
,
Tanay Karnik
Intel, USA
,
Program Chairs:
Muhammad M. Khellah
Intel, USA
,
Renu Mehra
Synopsys, USA

Copyright © 2014 ACM.

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Published: 11 August 2014

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National Science Foundation

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ISLPED'14

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SIGDA

ISLPED'14: International Symposium on Low Power Electronics and Design

August 11 - 13, 2014

California, La Jolla, USA

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ISLPED '14 Paper Acceptance Rate 63 of 184 submissions, 34%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Li TRomaszkan WPamarti SGupta P(2023)REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328428942:12(4423-4435)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3284289
Chen ZMa YWang Z(2022)Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.316652469:7(2707-2720)Online publication date: Jul-2022
https://doi.org/10.1109/TCSI.2022.3166524
Romaszkan WLi TGupta P(2022)SASCHA—Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319750341:11(4169-4180)Online publication date: Nov-2022
https://doi.org/10.1109/TCAD.2022.3197503
Wong MChen LDo A(2022)An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency DesignVLSI-SoC: Technology Advancement on SoC Design10.1007/978-3-031-16818-5_12(245-266)Online publication date: 22-Sep-2022
https://doi.org/10.1007/978-3-031-16818-5_12
Wong MChen LDo A(2021)A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC53125.2021.9606972(1-6)Online publication date: 4-Oct-2021
https://doi.org/10.1109/VLSI-SoC53125.2021.9606972
Sousa L(2021)Nonconventional Computer Arithmetic Circuits, Systems and ApplicationsIEEE Circuits and Systems Magazine10.1109/MCAS.2020.302742521:1(6-40)Online publication date: Sep-2022
https://doi.org/10.1109/MCAS.2020.3027425
Wu CShan WXu J(2019)ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)10.1109/NANOARCH47378.2019.181283(1-6)Online publication date: Jul-2019
https://doi.org/10.1109/NANOARCH47378.2019.181283
Li RNaous RFariborzi HSalama K(2019)Approximate Computing With Stochastic Transistors’ Voltage Over-ScalingIEEE Access10.1109/ACCESS.2018.28897477(6373-6385)Online publication date: 2019
https://doi.org/10.1109/ACCESS.2018.2889747
Betzel FKhatamifard KSuresh HLilja DSartori JKarpuzcu U(2018)Approximate CommunicationACM Computing Surveys10.1145/314581251:1(1-32)Online publication date: 10-Jan-2018
https://dl.acm.org/doi/10.1145/3145812
Lee VAlaghi APamula RSathe VCeze LOskin M(2018)Architecture Considerations for Stochastic Computing AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.285833837:11(2277-2289)Online publication date: Nov-2018
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