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Cofactor Sharing for Reversible Logic Synthesis

Published: 18 November 2014 Publication History

Abstract

Improving circuit realization of known quantum algorithms by CAD techniques has benefits for quantum experimentalists. In this article, the problem of synthesizing a given function on a set of ancillea is addressed. The proposed approach benefits from extensive sharing of cofactors among cubes that appear on function outputs. Accordingly, it can be considered a multilevel logic optimization technique for reversible circuits. In particular, the suggested approach can efficiently implement any n-input, m-output lookup table (LUT) by a reversible circuit. This problem has interesting applications in the Shor's number-factoring algorithm and in quantum walk on sparse graphs. Simulation results reveal that the proposed cofactor-sharing synthesis algorithm has a significant impact on reducing the size of modular exponentiation circuits for Shor's quantum factoring algorithm, oracle circuits in quantum walk on sparse graphs, and the well-known MCNC benchmarks.

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  • (2022)Heuristic Reordering Strategy for Quantum Circuit Mapping on LNN ArchitecturesComputational Intelligence and Neuroscience10.1155/2022/17659552022Online publication date: 1-Jan-2022
  • (2016)Ancilla-free synthesis of large reversible functions using binary decision diagramsJournal of Symbolic Computation10.1016/j.jsc.2015.03.00273:C(1-26)Online publication date: 1-Mar-2016
  • (2014)Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits PatternsProceedings of the 2014 17th Euromicro Conference on Digital System Design10.1109/DSD.2014.106(708-711)Online publication date: 27-Aug-2014

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    cover image ACM Journal on Emerging Technologies in Computing Systems
    ACM Journal on Emerging Technologies in Computing Systems  Volume 11, Issue 2
    Special Issue on Reversible Computation and Regular Papers
    November 2014
    199 pages
    ISSN:1550-4832
    EISSN:1550-4840
    DOI:10.1145/2686762
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Publication History

    Published: 18 November 2014
    Accepted: 01 April 2014
    Revised: 01 December 2013
    Received: 01 September 2013
    Published in JETC Volume 11, Issue 2

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    Author Tags

    1. Reversible logic
    2. automatic synthesis
    3. cofactor sharing
    4. design aids
    5. hardware
    6. logic design
    7. logic synthesis

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    Cited By

    View all
    • (2022)Heuristic Reordering Strategy for Quantum Circuit Mapping on LNN ArchitecturesComputational Intelligence and Neuroscience10.1155/2022/17659552022Online publication date: 1-Jan-2022
    • (2016)Ancilla-free synthesis of large reversible functions using binary decision diagramsJournal of Symbolic Computation10.1016/j.jsc.2015.03.00273:C(1-26)Online publication date: 1-Mar-2016
    • (2014)Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits PatternsProceedings of the 2014 17th Euromicro Conference on Digital System Design10.1109/DSD.2014.106(708-711)Online publication date: 27-Aug-2014

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