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A Resource-Efficient Design for a Reversible Floating Point Adder in Quantum Computing

Published: 18 November 2014 Publication History

Abstract

Reversible logic has applications in low-power computing and quantum computing. However, there are few existing designs for reversible floating-point adders and none suitable for quantum computation. In this article, we propose a resource-efficient reversible floating-point adder, suitable for binary quantum computation, improving the design of Nachtigal et al. [2011]. Our work focuses on improving the reversible designs of the alignment unit and the normalization unit, which are the most expensive parts. By changing a few elements of the existing algorithm, including the circuit designs of the RLZC (reversible leading zero counter) and converter, we have reduced the cost by about 68%. We also propose quantum designs adapted to use gates from fault-tolerant libraries. The KQ for our fault-tolerant design is almost 60 times as expensive as for a 32-bit fixed-point addition. We note that the floating-point representation makes in-place, truly reversible arithmetic impossible, requiring us to retain both inputs, which limits the sustainability of its use for quantum computation.

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      cover image ACM Journal on Emerging Technologies in Computing Systems
      ACM Journal on Emerging Technologies in Computing Systems  Volume 11, Issue 2
      Special Issue on Reversible Computation and Regular Papers
      November 2014
      199 pages
      ISSN:1550-4832
      EISSN:1550-4840
      DOI:10.1145/2686762
      Issue’s Table of Contents
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      Publication History

      Published: 18 November 2014
      Accepted: 01 April 2014
      Revised: 01 January 2014
      Received: 01 September 2013
      Published in JETC Volume 11, Issue 2

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      Author Tags

      1. IEEE-754 specification
      2. Reversible circuit
      3. floating-point arithmetic
      4. low-power computing
      5. nano technology
      6. quantum computing

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