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View all- Chua SSingh A(2019)Search-Based Reversible Logic Synthesis Using Mixed-Polarity GatesDesign and Testing of Reversible Logic10.1007/978-981-13-8821-7_6(93-113)Online publication date: 28-Jul-2019
A Synthesis Algorithm for 4-Bit Reversible Logic Circuits with Minimum Quantum Cost
Article No.: 29, Pages 1 - 19
Abstract
This article presents an algorithm which can quickly find the exact minimum solution to almost all of 4-bit reversible functions. We assume minimization of quantum cost (MQC). This algorithm is designed in the most memory-efficient way, or it will quickly run out of memory. Therefore, we construct the shortest coding of permutations, the topological compression and flexible data structures for the memory savings. First, hash tables are used for all 8-gate 4-bit circuits with the minimization of gate count (MGC) by using the GT library (with NOT, CNOT, Toffoli and Toffoli-4 gates). Second, we merge and split the hash tables, thus generating a single longer hash table for high-performance. Third, we synthesize these circuits with MQC by using the GTP library (with GT, Peres, and Inverted Peres gates) based on the hash table. Finally, according to the comparison of the QC of circuits, the algorithm can quickly converge for any 4-bit reversible circuit with MQC. By synthesizing all benchmark functions, in comparison with Szyprowski and Kerntopf [2011], the running time and QC are reduced up to 99.95% and 18.2%, respectively.
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Index Terms
- A Synthesis Algorithm for 4-Bit Reversible Logic Circuits with Minimum Quantum Cost
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Published In
December 2014
219 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/2711453
- Editor:
- Krishnendu Chakrabarty
Copyright © 2014 ACM.
© 2014 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.
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Association for Computing Machinery
New York, NY, United States
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Publication History
Published: 30 December 2014
Accepted: 01 April 2014
Revised: 01 December 2013
Received: 01 September 2013
Published in JETC Volume 11, Issue 3
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- National Natural Science Foundation of China
- Natural Science Foundation of College of Jiangsu Province
- Specialized Research Fund for the Doctoral Program of Higher Education
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Cited By
View all- Chua SSingh A(2019)Search-Based Reversible Logic Synthesis Using Mixed-Polarity GatesDesign and Testing of Reversible Logic10.1007/978-981-13-8821-7_6(93-113)Online publication date: 28-Jul-2019
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