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The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator

Published: 24 September 2015 Publication History

Abstract

Gaussian random number generators (GRNGs) are an important component in parallel Monte Carlo simulations using FPGAs, where tens or hundreds of high-quality Gaussian samples must be generated per cycle using very few logic resources. This article describes the Table-Hadamard generator, which is a GRNG designed to generate multiple streams of random numbers in parallel. It uses discrete table distributions to generate pseudo-Gaussian base samples, then a parallel Hadamard transform to efficiently apply the central limit theorem. When generating 64 output samples, the Table-Hadamard requires just 130 slices per generated sample, which is a third of the resources needed by the next best technique, while still providing higher statistical quality.

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    Published In

    cover image ACM Transactions on Reconfigurable Technology and Systems
    ACM Transactions on Reconfigurable Technology and Systems  Volume 8, Issue 4
    October 2015
    134 pages
    ISSN:1936-7406
    EISSN:1936-7414
    DOI:10.1145/2822909
    • Editor:
    • Steve Wilton
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 24 September 2015
    Accepted: 01 April 2014
    Revised: 01 February 2014
    Received: 01 September 2013
    Published in TRETS Volume 8, Issue 4

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    Author Tags

    1. Arithmetic operations
    2. parallel algorithms
    3. reconfigurable applications

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    • (2023)An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box–Muller MethodIEEE Access10.1109/ACCESS.2023.328943211(64745-64757)Online publication date: 2023
    • (2023)FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query ProcessingApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-031-42921-7_8(115-130)Online publication date: 16-Sep-2023
    • (2021)An Optimized FPGA Based Box-Muller Gaussian Random Number Generator Architecture for Communication Applications2021 IEEE 12th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)10.1109/IEMCON53756.2021.9623205(0772-0777)Online publication date: 27-Oct-2021
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    • (2016)A Domain Specific Language for accelerated Multilevel Monte Carlo simulations2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP.2016.7760778(99-106)Online publication date: Jul-2016

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