research-article

WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture

Authors:

Yoon Seok Yang,

Paul V. GratzAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 19, Issue 4

Article No.: 34, Pages 1 - 22

https://doi.org/10.1145/2647950

Published: 29 August 2014 Publication History

Abstract

WaveSync is a network-on-chip architecture for a globally asynchronous locally-synchronous (GALS) design. The WaveSync design facilitates low-latency communication leveraging the source-synchronous clock sent along with the data to time components in the datapath of a downstream router, reducing the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock domains, each synchronized with one of the orthogonal incoming source-synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router synchronously until the destination is reached, regardless of the number of hops this may take. As long as the data travels in the path of clock propagation and no congestion is encountered, it will be propagated without latching as if in a long combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with the typical GALS network is completely eliminated. To further reduce the latency overhead of synchronization, for those occasions when synchronization is still required (when a flit takes a turn or arrives at the destination), we propose a novel less-than-one-cycle synchronizer. The proposed WaveSync network outperforms conventional GALS networks by 87--90% in average latency, synthesized using a 45nm CMOS library.

References

[1]

M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, and L. Lavagno. 2005. Asynchronous on-chip networks. IEE Proc. Comput. Digital Techniq. 152, 2, 273--283.

[2]

W. P. Burleson, M. Ciesielski, F. Klass, and W. Liu. 1998. Wave-pipelining: A tutorial and research survey. IEEE Trans. VLSI Syst. 6, 3.

Digital Library

[3]

W. J. Dally. 1990. Performance analysis of k-ary n-cube interconnection networks. IEEE Trans. Comput. 39, 6, 775--785.

Digital Library

[4]

W. J. Dally. 1991. Express cubes: Improving the performance of k-ary n-cube interconnection networks. IEEE Trans. Comput. 40, 9, 1016--1023.

Digital Library

[5]

W. J. Dally and J. Poulton. 1998. Digital Systems Engineering. Cambridge University Press.

Digital Library

[6]

W. J. Dally and B. Towles. 2001. Route packets, not wires: On-chip interconnection networks. In Proceedings of the Design Automation Conference. 684--689.

Digital Library

[7]

W. J. Dally and B. Towles. 2003. Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Fransisco.

Digital Library

[8]

M. Donno, E. Macii, and L. Mazzoni. 2004. Power-aware clock tree planning. In Proceedings of the International Symposium on Physical Design. 138--147.

Digital Library

[9]

G. Gill, S. S. Attarde, G. Lacourba, and S. M. Nowick. 2011. A low latency adaptive asynchronous interconnection network using bi-modal router nodes. In Proceedings of the 5^th IEEE/ACM International Symposium on Networks on Chip (NoCS'11). 193--200.

Digital Library

[10]

P. Gratz and S. W. Keckler. 2010. Realistic workload characterization and analysis for networks-on-chip design. In Proceedings of the 4^th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI'10).

[11]

P. Gratz, C. Kim, R. Mcdonald, S. W. Keckler, and D. Burger. 2006. Implementation and evaluation of on-chip network architectures. In Proceedings of the IEEE International Conference on Computer Design (ICCD'06).

[12]

B. Grot, J. Hestness, S. W. Keckler, and O. Mutlu. 2009. Express cube topologies for on-chip interconnects. In Proceedings of the International Symposium on High Performance Computer Architecture. 163--174.

[13]

A. Hatakeyama, H. Mochizuki, T. Aikawa, M. Takiia, Y. Ishii, H. Tsuboi, S. Fujioka, S. Yamaguchi, M. Koga, Y. Serizawa, K. Nishimura, K. Kawabata, Y. Okajima, M. Kawano, H. Kojima, K. Mizutani, T. Anezaki, M. Hasegawa, and M. Taguchi. 1997. A 256 mb sdram using a register-controlled digital dll. In Proceedings of the International Solid-State Circuits Conference. 72--73.

[14]

A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilsson, J. Oberg, P. Ellervee, and D. Lundqvist. 1999. Lowering power consumption in clock by using globally asynchronous locally synchronous design style. In Proceedings of the 36^th Design Automation Conference. 873--878.

Digital Library

[15]

S. J. Hollis and C. Jackson. 2010. Skip the analysis: Self-optimising networks-on-chip. In Proceedings of the International Symposium on Electronic System Design (ISED'10). 14--19.

Digital Library

[16]

M. N. Horak, S. M. Nowick, M. Carlberg, and U. Vishkin. 2011. A low-overhead asynchronous interconnection network for gals chip multiprocessors. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 30, 4, 494--507.

Digital Library

[17]

International Technology Roadmap for Semiconductors. 2012. http://www.itrs.net/Links/2012ITRS/Home2012.htm.

[18]

T. N. K. Jain, P. V. Gratz, A. Sprintson, and G. Choi. 2010. Asynchronous bypass channels: Improving performance for multi-synchronous nocs. In Proceedings of the International Symposium on Networks-on-Chip. 51--58.

Digital Library

[19]

J. Kim. 2009. Low-cost router microarchitecture for on-chip networks. In Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture. 255--266.

Digital Library

[20]

J. Kim, W. J. Dally, B. Towles, and A. K. Gupta. 2005a. Microarchitecture of a high radix router. In Proceedings of the International Symposium on Computer Architecture. 420--431.

Digital Library

[21]

J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das. 2005b. A low latency router supporting adaptivity for on-chip interconnects. In Proceedings of the Design Automation Conference. 559--564.

Digital Library

[22]

T. Krishna, A. Kumar, P. Chiang, M. Erez, and L. Peh. 2008. NoC with near-ideal express virtual channels using global-line communication. In Proceedings of the Symposium on High Performance Interconnects. 11--20.

Digital Library

[23]

R. Kumar, Y. S. Yang, and G. Choi. 2011. Intra-flit skew reduction for asynchronous bypass channel in nocs. In Proceedings of the 24^th International Conference on VLSI Design. 238--243.

Digital Library

[24]

R. Mullins, A. West, and S. Moore. 2004. Low-latency virtual-channel routers for on-chip networks. In Proceedings of the 31^st Annual International Symposium on Computer Architecture. 188--197.

Digital Library

[25]

U. Ogras and R. Marculescu. 2005. Application-specific network-on-chip architecture customization via long-range link insertion. In Proceedings of the International Conference on Computer-Aided Design. 246--253.

Digital Library

[26]

I. M. Panades and A. Greiner. 2007. Bi-synchronous fifo for synchronous circuit communication well suited for network-on-chip in gals architectures. In Proceedings of the 5^th International Symposium on Networks-on-Chip. 83--94.

Digital Library

[27]

T. Saeki, K. Minami, H. Yoshida, and H. Suzuki. 1998. The direct skew detect synchronous mirror delay (direct smd) for asics. In Proceedings of the Custom Integrated Circuits Conference. 511--514.

[28]

Synopsys. 2012. RTL synthesis and test. http://www.synopsys.com/tools/implementation/rtlsynthesis/pages/default.aspx.

[29]

A. T. Tran, D. N. Truong, and B. M. Baas. 2009. A low-cost high-speed source-synchronous interconnection technique for gals chip multiprocessors. In Proceedings of the International Symposium on Circuits and Systems. 996--999.

[30]

S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, Iyer, P., A. Singh, A., T. Jacob, S. Jain, S. Venkataraman, Y. Hoskote, and N. Borkar. 2007. An 80-tile 1.28tflops network-on-chip in 65nm cmos. In Proceedings of the Solid-State Circuits Conference. 98--589.

[31]

S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. 1995. The splash-2 programs: Characterization and methodological considerations. In Proceedings of the Annual International Symposium on Computer Architecture.

Digital Library

[32]

Xilinx. 2009. Power consumption at 40 and 45nm. http://www.xilinx.com/support/documentation/white_papers/wp298.pdf.

Cited By

Fischer SNajafi AGarcia-Ortiz A(2023)Wave-Pipelined Source-Synchronous Circuit-Switched Data Transmission2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST57943.2023.10176839(1-6)Online publication date: 28-Jun-2023
https://doi.org/10.1109/MOCAST57943.2023.10176839

Index Terms

WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. Hardware
  1. Integrated circuits
    1. Interconnect

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 19, Issue 4

August 2014

246 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2663459

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2014 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 29 August 2014

Accepted: 01 May 2014

Revised: 01 April 2014

Received: 01 January 2013

Published in TODAES Volume 19, Issue 4

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Cited By

Fischer SNajafi AGarcia-Ortiz A(2023)Wave-Pipelined Source-Synchronous Circuit-Switched Data Transmission2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST57943.2023.10176839(1-6)Online publication date: 28-Jun-2023
https://doi.org/10.1109/MOCAST57943.2023.10176839

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