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Low energy memory and register allocation using network flow

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Published:13 June 1997Publication History

ABSTRACT

This paper presents for the first time low energy simultaneousmemory and register allocation. A minimum cost network flowapproach is used to efficiently solve for minimum energy dissipationsolutions in polynomial time. Results show that estimatedenergy improvements of 1.4 to 2.5 times over previous researchare obtained. This research is important for industry since energydissipation is minimized without requiring an increase in cost.

References

  1. 1.K.Keutzer, "The Impact of CAD on the Design of Low Power Digital Circuits", IEEE Symposium on Low Power Electronics, 1994, p42-45.Google ScholarGoogle ScholarCross RefCross Ref
  2. 2.S.Wuytack,F.Catthoor,F.Franssen,L.Nachtergaele, H.DeMan, "Global Communication and Memory Optimizing Transformations For Low Power Systems", International Workshop on Low Power Design, 1994, p 203-208.Google ScholarGoogle Scholar
  3. 3.A.Chandrakasan,et.al."Optimizing Power Using Transformations", IEEE Transactions on CAD, Jan 1995,Vol14,No.1, p12- 31. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. 4.A.Farrahi, G.Tellez,M.Sarrafzadeh, "Memory Segmentation to Exploit Sleep Mode Operation", Design Automation Conference, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. 5.Garey and Johnson,Computers and Intractability New York Freeman and Co 1979. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. 6.G.Chaitin, "Register Allocation & Spilling via Graph Coloring", ACM SIGPLAN Symp on Compiler Construction, 1982 Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. 7.F.Chow,J.Hennessey, "The Priority-Based Coloring Approach to Register Allocation", ACM Transactions on Programming Languages and Systems, p501-536, Oct 1990. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. 8.J.Chang, M.Pedram, "Register Allocation and Binding for Low Power", Design Automation Conference, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. 9.V.Tiwari, S.Malik,A.Wolfe, "Power Analysis of Embedded Software ;A First Step Towards Software Power Minimization, IEEE Trans on VLSI, Vol. 2, No. 4, Dec 1994, p437-445, Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. 10.D.Kolson,A.Nicolau,N.Dutt,K.Kennedy, "Optimal Register Allocation to Loops for Embedded Code Generation", International Symposium on Systems Synthesis, p42-47, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. 11.S.Wuytack,F.Catthoor,L.Nachtergaele,H.DeMan, "Power Exploration for Data Dominated Video Applications", ISLPED, p359-364, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. 12.W.Cheng, Y-L.Lin, "A Transformation-Based Approach for Storage Optimization", ACM/IEEE Design Automation Conference, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. 13.P.Landman, J.Rabaey, "Activity-Sensitive Architectural Power Analysis", IEEE Transactions on CAD,Vol.15,No.6, June 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. 14.P.A.Beerel, USC, Panel Presentation on "Where Does the Power GOT" at International Symposium on Low Power Design, April 1995.Google ScholarGoogle Scholar
  15. 15.Lee,Tiwari, "A Memory Allocation Technique for Low- Energy Embedded DSP Software", Symposium on Low Power Electronics, Oct, 1995, p24-5.Google ScholarGoogle Scholar
  16. 16.Lidsky,Rabaey, "Low-Power Design of Memory Intensive Functions", IEEE Symposium on Low Power Electronics, 1994, p16-7.Google ScholarGoogle Scholar
  17. 17.Nemhauser, Wolsey, Integer and Combinatorial Optimization, New York Wiley Interscience, 1988. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. 18.H.Schmitt,D.Thomas, "Array Mapping in Behavioral Synthesis ", Int'l Symp on Systems Synthesis, 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. 19.P.Panda, N.Dutt, "Low Power Mapping of Behavioral Arrays to Multiple Memories", Int'l Symp on Low Power Electronic Design, p289-292, 1996. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. 20.C.Gebotys, "Low Energy Memory Component Design for Cost-Sensitive High Performance Embedded Systems", IEEE Custom Integrated Circuits Conference, p397-400, 1996.Google ScholarGoogle ScholarCross RefCross Ref
  21. 21.C.Gebotys,R.Gebotys, "Performance-Power Optimization of Memory Components for Complex Embedded Systems", IEEE, 30th Hawaii International Conference on System Sciences, ECCS-6, Jan. 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library

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            • Published in

              cover image ACM Conferences
              DAC '97: Proceedings of the 34th annual Design Automation Conference
              June 1997
              788 pages
              ISBN:0897919203
              DOI:10.1145/266021

              Copyright © 1997 ACM

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              Publication History

              • Published: 13 June 1997

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              DAC '97 Paper Acceptance Rate139of400submissions,35%Overall Acceptance Rate1,770of5,499submissions,32%

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