ABSTRACT
A new technology re-mapping method named LDR (LayoutDriven Re-synthesis), which is applied after placement, is proposed.LDR executes re-mapping and re-placement simultaneouslyin order to minimize power consumption with placementinformation.High switching activity nets are concealed insidethe re-mapped cells or are shortened by re-placement in LDR.To estimate power consumption, LDR uses static power estimatorfor combinational circuits.LDR also calculates wirecapacitances accurately based on placement information toevaluate power.Experimental results show that 20% powerreduction compared with original circuits is performed by proposed method.
- 1.Kamal Chaudhary and Massoud Pedram : "A near optimal algorithm for technology mapping minimizing area under delay constraints", Proc. Desi9n Automation Conf., pp. 492- 498 (1992). Google ScholarDigital Library
- 2.Chi-Ying Tsui, Massoud Pedram and Alvin M. DespMn : "Technology decomposition and mapping targeting low power dessipation', Proc. Desi9n Automation Conf., pp. 68-73 (1993). Google ScholarDigital Library
- 3.De-Sheng Chen and Majid Sarrafzadeh : "An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing", Proc. Desi9n Automation Conf., pp. 782-788 (1996). Google ScholarDigital Library
- 4.H. Vaishnav and Massoud Pedram : "Pcube:A Performance Driven Placement Algorithm for Low Power Designs", Proc. European Desi9n Automation Conf., pp. 72-77 (1993).Google Scholar
- 5.Massoud Pedram and Narasimha Bhat : "Layout driven technology mapping", Proc. Desi9n Automation Conf., pp. 99-105 (1991). Google ScholarDigital Library
- 6.Lalgudi N. Kannan, Peter R. Suaris and Hong-Gee Fang : "A methodology and algorithms for post-placement delay optimization", Proc. Desi9n Automation Conf., pp. 327-332 (1994). Google ScholarDigital Library
- 7.Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi and Nobuyuki Goto : "Switching activity using boolean approximation method", Proc. Desi9n Automation Conf., pp. 20- 25 (1995). Google ScholarDigital Library
- 8.Mutsunori Igarashi, Masako Murofushi and Masami Murakata, "Timing Divert Placement with an RC wire Delay Model for Sub-Micron CMOS Gate-Arrays", SASIMI '93. (1993).Google Scholar
Index Terms
- Layout driven re-synthesis for low power consumption LSIs
Recommendations
Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique
VLSID '97: Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia ApplicationsWith the increasing use of portable computing and wireless communication systems, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Towards this end we introduce algebraic procedures for node extraction ...
Low Power Gated Clock Tree Driven Placement
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the most effective methods is based on clock gating to shut off the clock when ...
Comments