skip to main content
10.1145/2660540.2661013acmconferencesArticle/Chapter ViewAbstractPublication PagessbcciConference Proceedingsconference-collections
tutorial

Hardware/software debugging of large scale many-core architectures

Published: 01 September 2014 Publication History

Abstract

The size of current multi-processor system-on-chip (MPSoC) is growing unsustainable. Besides, new decentralized software approaches are being developed to handle the management of increasing resources. To verify the system functionality of these novel hardware/software systems, sufficiently accurate models are required. However, current simulation tools have limited scalability and performance; hence hardware prototypes and debugging concepts are necessary for system verification.
We present a novel debug approach which offers visualization of hardware/software interaction for system level verification. The debug concept comprises debug probes within each router of the network as well as monitoring units to trace the activity of each core in the MPSoC. In addition a transactor based method is proposed to transmit the huge amount of debug information out of the hardware prototype to evaluate the information on a standard host computer. Experimental results show that the resource overhead is insignificant in contrast to the gain of extensive debug possibilities. Furthermore the number of pins required for the presented debugging concept is kept constant independent of the architecture size and thus we are not facing problems of limited debug interfaces or pins. In comparison to conventional debugging we show improvements in scalability and bandwidth.

References

[1]
Synopsys. (2013) Synopsys haps-70 series. {Online}. Available: http://www.synopsys.com
[2]
"S2c v7 tai logic module." {Online}. Available: http://www.s2cinc.com/Product.htm
[3]
C. Ciordas, T. Basten, A. Radulescu, K. Goossens, and J. Meerbergen, "An event-based network-on-chip monitoring service," in High-Level Design Validation and Test Workshop, 2004. Ninth IEEE International, Nov. 2004, pp. 149--154.
[4]
B. Vermeulen and K. Goossens, "A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs," in International Symposium on VLSI Design, Automation and Test, 2009. VLSI-DAT '09, Apr. 2009, pp. 183--186.
[5]
G. Fey and M. Dehbashi, "Transaction-based online debug for noc-based multiprocessor socs," 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, vol. 0, pp. 400--404, 2014.
[6]
P. Bomel, K. Martin, and J.-P. Diguet, Virtual UARTs for Reconfigurable Multi-processor Architectures, ser. IPDPSW '13. Washington, DC, USA: IEEE Computer Society, 2013.
[7]
S. Boppu, V. Lari, F. Hannig, and J. Teich, "Transactor-based prototyping of heterogeneous multiprocessor system-on-chip architectures," in Proceedings of the Synopsys Users Group Conference (SNUG), 2013.
[8]
J. Teich, J. Henkel, A. Herkersdorf, D. Schmitt-Landsiedel, W. Schröder-Preikschat, and G. Snelting, "Invasive computing: An overview," in Multiprocessor System-on-Chip. Springer, 2011.
[9]
J. Heisswolf, A. Zaib, A. Zwinkau, S. Kobbe et al., "CAP: Communication aware programming," in Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, ser. DAC '14. New York, NY, USA: ACM, 2014, pp. 105:1--105:6.
[10]
J. Heisswolf, A. Zaib, A. Weichslgartner et al., "The invasive network on chip - a multi-objective many-core communication infrastructure," in 2014 27th International Conference on Architecture of Computing Systems (ARCS), 2014.
[11]
J. Heisswolf, R. König, M. Kupper, and J. Becker, "Providing multiple hard latency and throughput guarantees for packet switching networks on chip," Computers & Electrical Engineering, 2013.
[12]
J. Heisswolf, R. Konig, and J. Becker, "A scalable NoC router design providing QoS support using weighted round robin scheduling," in 2012 IEEE 10th International Symposium on Parallel and Distributed Processing with Applications (ISPA), Jul. 2012, pp. 625--632.
[13]
A. Gaisler. (2013) GRLIB IP Core User's Manual. {Online}. Available: http://www.gaisler.com/products/grlib/grip.pdf
[14]
A. Gaisler. (2014) GRMON2 User's Manual. {Online}. Available: http://www.gaisler.com/doc/grmon2.pdf
[15]
J. Becker, S. Friederich, J. Heisswolf, R. Koenig, and D. May, "Hardware prototyping of novel invasive multicore architectures," in Design Automation Conference (ASP-DAC), 17th Asia and South Pacific, 2012.
[16]
Xactors reference, www.synopys.com, 2013.

Cited By

View all
  • (2019)Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon EraIEEE Access10.1109/ACCESS.2019.29004777(33115-33129)Online publication date: 2019

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
SBCCI '14: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design
September 2014
286 pages
ISBN:9781450331562
DOI:10.1145/2660540
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 2014

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. Many-Core
  2. Network on Chip
  3. Prototyping

Qualifiers

  • Tutorial
  • Research
  • Refereed limited

Conference

SBCCI '14
Sponsor:

Acceptance Rates

SBCCI '14 Paper Acceptance Rate 40 of 130 submissions, 31%;
Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)6
  • Downloads (Last 6 weeks)1
Reflects downloads up to 15 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2019)Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon EraIEEE Access10.1109/ACCESS.2019.29004777(33115-33129)Online publication date: 2019

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media