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Execution Trace--Driven Energy-Reliability Optimization for Multimedia MPSoCs

Published: 04 May 2015 Publication History

Abstract

Multiprocessor systems-on-chip (MPSoCs) are becoming a popular design choice in current and future technology nodes to accommodate the heterogeneous computing demand of a multitude of applications enabled on these platform. Streaming multimedia and other communication-centric applications constitute a significant fraction of the application space of these devices. The mapping of an application on an MPSoC is an NP-hard problem. This has attracted researchers to solve this problem both as stand-alone (best-effort) and in conjunction with other optimization objectives, such as energy and reliability. Most existing studies on energy-reliability joint optimization are static—that is, design time based. These techniques fail to capture runtime variability such as resource unavailability and dynamism associated with application behaviors, which are typical of multimedia applications. The few studies that consider dynamic mapping of applications do not consider throughput degradation, which directly impacts user satisfaction. This article proposes a runtime technique to analyze the execution trace of an application modeled as Synchronous Data Flow Graphs (SDFGs) to determine its mapping on a multiprocessor system with heterogeneous processing units for different fault scenarios. Further, communication energy is minimized for each of these mappings while satisfying the throughput constraint. Experiments conducted with synthetic and real SDFGs demonstrate that the proposed technique achieves significant improvement with respect to the state-of-the-art approaches in terms of throughput and storage overhead with less than 20% energy overhead.

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems
ACM Transactions on Reconfigurable Technology and Systems  Volume 8, Issue 3
May 2015
153 pages
ISSN:1936-7406
EISSN:1936-7414
DOI:10.1145/2770880
  • Editor:
  • Steve Wilton
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 04 May 2015
Accepted: 01 August 2014
Revised: 01 July 2014
Received: 01 October 2013
Published in TRETS Volume 8, Issue 3

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Author Tags

  1. Synchronous Data Flow Graphs
  2. Task mapping and scheduling
  3. energy consumption
  4. fault tolerance
  5. multimedia applications

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  • Research-article
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  • Refereed

Funding Sources

  • Singapore Ministry of Education Academic Research Fund Tier 1

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  • (2021)Software Compilation and Optimization Techniques for Heterogeneous Multi‐core PlatformsMulti‐Processor System‐on‐Chip 210.1002/9781119818410.ch10(203-235)Online publication date: 28-Apr-2021
  • (2020)Improving Dependability of Neuromorphic Computing With Non-Volatile Memory2020 16th European Dependable Computing Conference (EDCC)10.1109/EDCC51268.2020.00013(17-24)Online publication date: Sep-2020
  • (2018)A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00060(287-292)Online publication date: Jul-2018
  • (2018)A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systemsJournal of Systems Architecture10.1016/j.sysarc.2018.10.003Online publication date: Oct-2018
  • (2017)Robust Mapping of Process Networks to Many-Core Systems using Bio-Inspired Design CenteringProceedings of the 20th International Workshop on Software and Compilers for Embedded Systems10.1145/3078659.3078667(21-30)Online publication date: 12-Jun-2017
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  • (2017)ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip MultiprocessorsIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.26868563:2(72-85)Online publication date: 1-Apr-2017
  • (2017)MAPS: A Software Development Environment for Embedded Multi-core ApplicationsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_2-1(1-33)Online publication date: 21-Apr-2017
  • (2017)MAPS: A Software Development Environment for Embedded Multicore ApplicationsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_2(917-949)Online publication date: 27-Sep-2017
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